Stacked Semiconductor Package Test Pattern for Chip Spacing Detection
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Solution Overview
Problem
Current semiconductor packages lack an efficient method for testing structural defects, particularly unintended spacing between stacked semiconductor chips, which can lead to functional issues and reduced reliability.
Innovation Solution
A semiconductor package design that incorporates test patterns and vias to form a series circuit, allowing for easy detection of structural defects by connecting test pads in a daisy chain configuration, enabling the identification of spacing issues between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked vertically to achieve high-density integration, then the package capacity and integration density are improved, but the difficulty of detecting structural defects such as unintended spacing increases
Solution Approach 1:
The patent divides the test function into multiple test pads distributed across different chips in the stack. Each chip has its own test pads that can be independently connected through vertical vias, allowing segmented testing of each chip-to-chip interface rather than requiring complete disassembly of the stacked package.
Solution Approach 2:
The patent introduces test pads and via structures as intermediary elements between the chips and the testing equipment. These intermediaries provide accessible test points on the package exterior that connect to internal chip interfaces, enabling external detection of internal bonding defects without direct observation of the chip interfaces.
2Device complexity
If conventional semiconductor packages are designed without integrated test patterns, then the device complexity is reduced, but the ease of operation for testing structural defects deteriorates
Solution Approach 1:
The patent incorporates test pads and test patterns during the chip fabrication process itself, before the chips are stacked and packaged. This preliminary preparation of test structures allows for easy subsequent testing without requiring additional complex equipment or procedures after packaging.
Solution Approach 2:
The test pads serve multiple functions: they enable electrical connection for signal transmission, provide test points for detecting bonding defects, and allow verification of via connectivity. This multi-functionality reduces the need for separate dedicated test structures.
3Measurement precision
If test pads are configured in a series circuit pattern, then the measurement precision for detecting spacing defects is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple test functions into a unified series circuit pattern. By connecting test pads through vias in a sequential daisy-chain arrangement, the design uses a single continuous electrical path to test multiple chip interfaces, reducing the need for separate independent test circuits for each interface.
Solution Approach 2:
The patent changes the electrical parameters (resistance, continuity) of the test circuit to reflect the physical spacing conditions between chips. When chips are properly bonded, the electrical parameters fall within expected ranges; when spacing defects occur, the parameters change detectably, providing precise measurement of bonding quality.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip on a substrate and including a first semiconductor substrate and a first test pattern on a first surface of the first semiconductor substrate, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor substrate and a second test pattern on a second surface of the second semiconductor substrate. The first and second semiconductor chips bonded to allow the first test pattern to face the second test pattern. The first test pattern includes a first in-pad, first connection pads, and a first out-pad. The second test pattern includes a second in-pad bonded to the first in-pad, a second out-pad bonded to the first out-pad, and second connection pads bonded to the first connection pads. The first and second connection pads are connected in series to alternately connect with each other and form a series wiring pattern, so that each first connection pad connects to another first connection pad in one direction along the series wiring pattern and to a second connection pad in an opposite direction along the series wiring pattern.