Stacked Semiconductor Package With Stepped Metal Posts for Reliable Bonding
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving small physical size, high performance, and high capacity while maintaining reliability and manufacturing productivity, particularly in the integration of semiconductor chips and redistribution structures.
Innovation Solution
The semiconductor package design includes a first semiconductor chip with rear and front pads connected by through-electrodes, a second semiconductor chip with wider dimensions, and a redistribution structure with metal posts that connect the second chip to the redistribution layers, featuring varying widths and positions to enhance electrical connectivity and structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second semiconductor chip has a greater width than the first semiconductor chip to enhance electrical connectivity, then the electrical connection reliability is improved, but the overall package size increases
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration. The second semiconductor chip is positioned above the first chip, and metal posts extend vertically to connect the second chip's second connection pads to the redistribution structure below, utilizing the vertical dimension to achieve enhanced connectivity without proportionally increasing the horizontal package footprint.
Solution Approach 2:
The patent implements a nested arrangement where the first semiconductor chip is positioned within the horizontal footprint of the second semiconductor chip. The redistribution structure and metal posts are nested within the overall package structure, allowing multiple functional elements to occupy overlapping spatial regions and reducing the total package area.
2Reliability
If metal posts with varying widths are used to prevent damage and enhance structural stability, then the manufacturing reliability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The metal posts exhibit local quality variations in their cross-sectional widths along their length. The first portion has a first width and the second portion has a second width greater than the first width, creating a stepped or tapered structure. This local variation provides structural reinforcement at critical regions without requiring complete redesign of all metal posts, balancing improved reliability with manageable manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the reliability and productivity of semiconductor packages by enabling efficient thermal compression bonding, preventing damage to metal posts, and maintaining structural stability, thus addressing the challenges of size, performance, and capacity.
Implementation Method 1
through-electrodes electrically connecting the rear pads and the front pads
Implementation Method 2
metal posts around the first semiconductor chip, extending between the redistribution structure and the second semiconductor chip, and electrically connecting the second connection pads of the second semiconductor chip and the second redistribution layers of the redistribution structure
Implementation Method 3
enabling efficient thermal compression bonding
Data Source
AI summary
A semiconductor package includes; a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a redistribution structure below the first semiconductor chip, and metal posts around the first semiconductor chip, extending between the redistribution structure and the second semiconductor chip, and electrically connecting the second semiconductor chip and redistribution structure, wherein the metal posts include an arrangement of first metal posts spaced apart around the first semiconductor chip, and an arrangement of second metal posts spaced apart around the arrangement of first metal posts, and each of the first metal posts in the arrangement of first metal posts includes a portion having a width greater than a width of each of the second metal posts.


