Stacked Semiconductor Package Stiffener for Warpage Control
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Solution Overview
Problem
Current semiconductor packages face challenges in enhancing reliability and durability, particularly in managing thermal expansion and warpage issues.
Innovation Solution
A semiconductor package design incorporating a stiffener structure with sequentially stacked first and second stiffeners made of different materials, where the second stiffener has a wider width and a higher coefficient of thermal expansion, effectively surrounding the chip and peripheral structures to alleviate physical stress and maximize bonding area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-layer stiffener structure is used, then the structure is simple and easy to manufacture, but it cannot effectively suppress warpage and control thermal expansion
Solution Approach 1:
The stiffener structure is divided into multiple layers (first stiffener layer, second stiffener layer, third stiffener layer) with different materials and properties. Each layer segments the thermal expansion management function, allowing independent optimization of each layer's material characteristics to match different thermal zones of the semiconductor package.
Solution Approach 2:
The patent employs composite material construction where each stiffener layer uses different materials with distinct coefficients of thermal expansion. The first layer uses a material with lower CTE than the substrate, the second layer matches the substrate CTE, and the third layer has higher CTE, creating a composite structure that collectively suppresses warpage through differential thermal expansion.
2Reliability
If stiffener width is increased to maximize bonding area, then bonding reliability improves, but the structure becomes more complex and manufacturing difficulty increases
Solution Approach 1:
Instead of increasing stiffener width in the planar dimension, the patent extends the stiffener structure into the vertical dimension by creating multiple stacked layers. This dimensional transition allows the stiffener to provide enhanced bonding area and structural support without increasing lateral footprint, thereby simplifying manufacturing while improving reliability.
Solution Approach 2:
The multiple stiffener layers are nested vertically one above another, with each layer contributing to the overall bonding area and structural integrity. This nesting arrangement maximizes the effective bonding area within a compact vertical space, avoiding the need for wider lateral extensions that would complicate manufacturing.
3Reliability
If uniform material is used throughout the stiffener structure, then manufacturing is simplified, but thermal expansion cannot be effectively managed across different regions
Solution Approach 1:
Each stiffener layer is assigned a specific material with tailored properties appropriate for its functional role. The first layer uses material with lower CTE for regions requiring thermal contraction, the second layer uses material matching substrate CTE for thermal compatibility, and the third layer uses material with higher CTE for regions requiring thermal expansion compensation. This local quality differentiation optimizes thermal expansion management.
Solution Approach 2:
The patent systematically varies the coefficient of thermal expansion parameter across different stiffener layers to match the thermal characteristics of different regions of the semiconductor package. By changing the material parameter (CTE) from layer to layer, the structure achieves effective thermal expansion management without requiring complex geometric modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses and controls warpage, improving the reliability and durability of semiconductor packages by optimizing thermal expansion management.
Implementation Method 1
a coefficient of thermal expansion of the first stiffener is smaller than a coefficient of thermal expansion of the second stiffener
Data Source
AI summary
A semiconductor package including a package substrate, a chip structure on the package substrate, a peripheral structure disposed on the package substrate and disposed around the chip structure, and a stiffener structure disposed at an edge of the package substrate and surrounding the peripheral structure and the chip structure. The stiffener structure includes a first stiffener and a second stiffener that are sequentially stacked, the second stiffener includes a material different from a material of the first stiffener, and the second stiffener has a second width wider than a first width of the first stiffener and vertically overlaps the peripheral structure.