Stacked Semiconductor Package With Dummy Chip Stress Buffering
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving a thin profile while maintaining electrical connectivity and structural integrity, particularly when subjected to external stress, which can lead to crack defects.
Innovation Solution
A semiconductor package design that includes a substrate, a first semiconductor chip electrically connected to the substrate, a second semiconductor chip stack with multiple chips stacked vertically and electrically connected, and a dummy third semiconductor chip positioned above the second chip stack, with specific bonding structures to manage stress and improve fabrication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are stacked in a vertical direction to reduce package volume, then the package volume is reduced, but the package becomes more susceptible to external stress and crack defects
Solution Approach 1:
A dummy third semiconductor chip is positioned over the second semiconductor chip stack to provide beforehand cushioning. This dummy chip acts as a protective element that absorbs external stress before it reaches the functional chips, preventing crack defects while maintaining the compact vertical stacking configuration
2Length of stationary object
If each semiconductor chip is made thin to achieve a thin package profile, then the package thickness is reduced, but the structural integrity and stress resistance deteriorate
Solution Approach 1:
The dummy third semiconductor chip provides beforehand cushioning that compensates for the reduced structural integrity of thin chips. By positioning this protective element at the top of the stack, the package achieves a thin profile while the dummy chip absorbs stress that would otherwise cause cracks in the thin functional chips
3Reliability
If a dummy third semiconductor chip is added to relieve stress, then stress resistance is improved, but the device complexity increases
Solution Approach 1:
The dummy third semiconductor chip functions as a disposable protective element that sacrifices itself to protect the valuable functional chips. This dummy chip is positioned to absorb stress and can be designed with simpler requirements, providing an cost-effective solution to enhance stress resistance without requiring complex modifications to the functional chip stack
Data Source
AI summary
A semiconductor package includes: a substrate; a first semiconductor chip positioned over the substrate and electrically connected to the substrate; a second semiconductor chip stack positioned over the first semiconductor chip and including a plurality of second semiconductor chips that are stacked in a vertical direction while being electrically connected to the first semiconductor chip; and a dummy third semiconductor chip positioned over the second semiconductor chip stack, wherein a third height of a third bonding structure coupling the third semiconductor chip to an uppermost second semiconductor chip among the second semiconductor chips is greater than a second height of a second bonding structure coupling one among the second semiconductor chips to an another one among the second semiconductor chips positioned directly therebelow or the first semiconductor chip positioned directly therebelow.