Stacked Semiconductor Package Structure for Substrate Integrity
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Solution Overview
Problem
The challenge is to prevent damage or deformation of the package substrate during the manufacturing process of semiconductor packages, particularly as the number of input/output pins increases and high-speed connection technologies are required.
Innovation Solution
A semiconductor package design that includes a first semiconductor chip with through-electrodes and a redistribution structure connected to conductive posts, bonded to a second semiconductor chip with a distinct interconnection structure, using mold layers and passivation layers to secure conductive connection structures, ensuring robust signal transmission and heat dissipation while minimizing structural degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through-electrodes and fine-bump connection technology are used to increase the number of input/output pins for high-speed integration, then connection density and signal transmission speed are improved, but the package substrate becomes more susceptible to damage and deformation during manufacturing
Solution Approach 1:
The patent applies beforehand cushioning by forming a protective mold layer over the conductive posts and interconnection structures before subsequent manufacturing steps. This mold layer acts as a cushioning protective layer that prevents damage and deformation of the fragile through-electrodes and fine-bump connections during chip stacking and processing, thereby maintaining substrate integrity while enabling high-density connections
2Productivity
If chip stacking structure is implemented to achieve high degree of integration, then the number of input/output pins increases, but the complexity of the manufacturing process increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the protective mold layer around the conductive posts and interconnection structures before chip stacking. This preliminary protective action simplifies the subsequent chip stacking process by eliminating the need for complex alignment and protection measures, as the mold layer is already in place to protect the delicate structures during integration
Solution Approach 2:
The mold layer serves as an intermediary protective element between the delicate through-electrodes/fine-bumps and the mechanical stresses of chip stacking. This intermediary structure enables high-degree integration by facilitating the chip stacking process without direct contact between stacking equipment and fragile connection structures
3Reliability
If conductive posts and mold layers are added to protect through-electrodes, then substrate integrity is improved, but device structure becomes more complex
Solution Approach 1:
The patent merges the protective function with the existing interconnection structure by forming the mold layer to surround the conductive posts and integrate with the interconnection layers. This merging approach provides substrate integrity protection while minimizing additional structural complexity, as the protective layer becomes an integrated part of the overall device architecture rather than a separate additive component
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first interconnection structure on first surface, through-electrodes connected to the first interconnection structure, a redistribution structure on a second surface and connected to the through-electrodes, and first contact pads on the redistribution structure, a second semiconductor chip including a second interconnection structure, the second semiconductor chip having a first region on which the first semiconductor chip is disposed, and second contact pads on the first region and bonded to the first contact pads, first conductive posts on the first interconnection structure, a first mold layer on the first interconnection structure and surrounding the first conductive posts, second conductive posts on the second region, a second mold layer on the second region and surrounding the second conductive posts, the first semiconductor chip, and the first molded layer, and a passivation layer on the first molded layer and the second molded layer.