Stacked Semiconductor Package with Protected Bumps and Thermal Voids
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving improved electrical properties and thermal radiation while maintaining a compact and functional design for smaller, lighter, and multifunctional electronic devices.
Innovation Solution
A semiconductor package design featuring a stack of semiconductor chips with connection bumps covered by a protection layer and a mold layer that includes a void, enhancing electrical connectivity and thermal radiation through a molded under-fill material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection bumps are exposed without protection, then electrical connectivity is maintained, but electrical shorts may occur between adjacent bumps
Solution Approach 1:
A protection layer is introduced as an intermediary substance between adjacent connection bumps. This layer selectively covers the lateral surfaces of the bumps while leaving their top surfaces exposed, thereby preventing electrical shorts between neighboring bumps while maintaining electrical connectivity through the bump tips.
2Strength
If mold layer completely fills all spaces, then structural support is maximized, but thermal radiation is reduced
Solution Approach 1:
The mold layer is applied selectively rather than uniformly throughout the entire package. It covers lateral surfaces of semiconductor chips and connection bumps for structural support, but intentionally leaves void spaces in certain regions to allow thermal radiation, achieving different functional qualities in different locations.
3Reliability
If multiple separate layers are used for protection and molding, then functional performance is improved, but fabrication complexity increases
Solution Approach 1:
The protection layer and mold layer are combined into a single integrated structure. The protection layer serves dual functions: it protects connection bumps from electrical shorts and simultaneously acts as a structural component within the overall mold assembly, reducing the number of separate fabrication steps required.
Data Source
AI summary
A semiconductor package includes a lower semiconductor chip and semiconductor chips in a stack on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip. Connection bumps are between the lower semiconductor chip and a bottommost one of the semiconductor chips and between the semiconductor chips, A protection layer covers a lateral surface of each of the connection bumps. A mold layer is on the lower semiconductor chip and covering lateral surfaces of the semiconductor chips. The mold layer extends between the bottommost one of the semiconductor chips and the lower semiconductor chip and between the semiconductor chips. The protection layer is between the mold layer and the lateral surface of each of the connection bumps.