Stacked Semiconductor Package Layout for Protected Through-Electrodes

Solution Overview

Problem

Existing semiconductor packages face challenges in miniaturization and yield improvement while maintaining high performance and capacitance, particularly in stacked semiconductor chip configurations using through-electrodes.

Innovation Solution

A semiconductor package design that includes a first semiconductor chip bonded to a second semiconductor chip with through-electrodes, surrounded by a first dielectric layer and a second dielectric layer, with bump structures for electrical connection, and a method of manufacturing that involves etching, plating, and polishing to form a planar surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through-electrodes are used to interconnect stacked semiconductor chips, then electrical connection between chips is achieved, but the manufacturing process becomes complex and yield decreases

Engineering Contradiction:

Improveelectrical connectionVSAvoidmanufacturing process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by forming a protective dielectric layer around the through-electrodes before the planarization process. This pre-protection measure prevents damage to the through-electrodes during subsequent manufacturing steps, simplifying the overall process and improving yield while maintaining reliable electrical connections between stacked chips.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements beforehand cushioning by introducing a dielectric layer that surrounds and protects the through-electrodes prior to planarization. This protective cushioning layer prevents mechanical damage to the through-electrodes during the polishing process, thereby simplifying manufacturing and improving yield without compromising electrical connection reliability.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If through-electrodes protrude from the substrate for electrical connection, then connection reliability is improved, but the through-electrodes are damaged during planarization

Engineering Contradiction:

Improveconnection reliabilityVSAvoidthrough-electrode integrity

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent implements beforehand cushioning by introducing a dielectric layer that surrounds and protects the through-electrodes prior to planarization. This protective cushioning layer prevents mechanical damage to the through-electrodes during the polishing process, thereby simplifying manufacturing and improving yield without compromising electrical connection reliability.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent uses a dielectric layer as an intermediary protective layer between the through-electrodes and the planarization process. This intermediary layer allows the planarization to proceed while protecting the through-electrodes from damage, maintaining both connection reliability and manufacturing precision.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If semiconductor chips are miniaturized for high performance and capacitance, then device performance is improved, but manufacturing complexity increases

Engineering Contradiction:

Improvedevice performanceVSAvoidmanufacturing complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming a protective dielectric layer around the through-electrodes before the planarization process. This pre-protection measure prevents damage to the through-electrodes during subsequent manufacturing steps, simplifying the overall process and improving yield while maintaining reliable electrical connections between stacked chips.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design simplifies the manufacturing process and improves yield by minimizing signal transmission paths and protecting through-electrodes during planarization, enhancing stability and reliability.

Implementation Method 1

forming a preliminary plating layer in the second opening; removing the resist layer and etching the preliminary seed layer

Methodology Applied

Scientific EffectElectroplating: Electroplating

Implementation Method 2

polishing the first preliminary dielectric layer, the preliminary plating layer, the second preliminary dielectric layer, and the plurality of preliminary through-electrodes, wherein a planar surface is formed

Methodology Applied

Scientific EffectMechanical polishing: Abrasion

Data Source

PatentUS12581931B2Semiconductor package and method of manufacturing the same

Publication Date: 2026.03.17 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes: a first semiconductor chip including first pads; a second semiconductor chip below the first semiconductor chip, the second semiconductor chip including a substrate including a front surface and an opposing rear surface, second pads on the front surface and in contact with the first pads, and through-electrodes electrically connected to the second pads and including protruding portions protruding from the rear surface of the substrate; through-via structures disposed around the second semiconductor chip and in contact with the first pads; a first dielectric layer extending along the rear surface of the substrate and side surfaces of the protruding portions of the through-electrodes; a second dielectric layer below the first dielectric layer and in a space between the protruding portions of the through-electrodes and between the through-via structures; and bump structures below the second dielectric layer and electrically connected to the through-electrodes and the through-via structures.