Stacked Semiconductor Package with Through Posts for Signal Integrity

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Solution Overview

Problem

Semiconductor packages face challenges in achieving high performance, capacity, and reliability while minimizing size, weight, and power consumption, with existing designs often resulting in inefficient signal transfer paths that affect heat management and signal integrity.

Innovation Solution

The semiconductor package design incorporates a first and second redistribution substrate, a through post, and an encapsulant to create a shortened signal transfer path between upper and lower chips, utilizing a nano through-electrode and upper wiring layer to connect the chips directly, thereby improving signal integrity and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the signal transfer path between upper and lower chips is shortened, then heat is reduced and signal integrity is improved, but the device structure becomes more complex requiring additional components like through posts and redistribution substrates

Engineering Contradiction:
ImproveheatVSAvoiddevice structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The device is segmented into multiple functional layers including first and second redistribution substrates, upper and lower chips, and through posts. This segmentation allows the signal path to be optimized independently in each layer, shortening the overall transfer path while managing complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The signal transfer path is transitioned from a planar configuration to a three-dimensional stacked architecture. By utilizing vertical stacking with through posts penetrating the substrate and redistribution layers, the signal path is shortened in the vertical dimension while the horizontal footprint remains compact

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If high performance and capacity are achieved through increased power consumption, then processing capability is improved, but power consumption increases which contradicts the goal of miniaturization and efficiency

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent replaces traditional long-distance electrical signal transmission through substrate traces with a direct vertical connection system using through posts and redistribution substrates. This substitution reduces signal path resistance and inductance, improving processing capability while reducing power consumption associated with signal transmission

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Volume of moving object

If the semiconductor package size is reduced to meet miniaturization requirements, then portability is improved, but the signal transfer path length may increase affecting signal integrity

Engineering Contradiction:
Improvepackage sizeVSAvoidsignal integrity
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent transitions from two-dimensional planar signal routing to three-dimensional vertical signal paths. By stacking chips and redistribution substrates vertically with through posts providing direct connections, the signal path is shortened in the vertical dimension allowing compact packaging while maintaining signal integrity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Redistribution substrates and through posts serve as intermediary structures that enable direct vertical signal transmission between upper and lower chips. These intermediaries provide controlled impedance paths and reduce signal degradation that would otherwise occur in longer horizontal traces required in larger packages

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240021579A1Semiconductor package and manufacturing method thereof
Publication Date: 2024.01.18 SAMSUNG ELECTRONICS CO LTD
  • US20240021579A1 patent drawing
  • US20240021579A1 patent drawing
  • US20240021579A1 patent drawing

AI summary

A semiconductor package having a signal transfer path between semiconductor chips and a method of manufacturing the semiconductor package are provided. The semiconductor package includes a first redistribution substrate, a semiconductor chip stack arranged on the first redistribution substrate and including a lower chip and an upper chip, a through post arranged on the first redistribution substrate around the semiconductor chip stack, and a second redistribution substrate arranged on the semiconductor chip stack and the through post. The upper chip includes a through-electrode arranged on an integrated circuit layer, and has a front surface, which is an active face and faces the lower chip, and a back surface, which is an inactive face and faces the second redistribution substrate.