Stacked Semiconductor Package Through-Via Layout for Warpage Control
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Solution Overview
Problem
Current semiconductor package technologies face challenges in achieving compact size and high performance, especially when multiple semiconductor chips are integrated, as fan-in packages are limited by spatial constraints and fan-out packages may not efficiently address warpage issues and thermal characteristics.
Innovation Solution
A semiconductor package design that includes a first and second package structure with redistribution layers connected via a through-via penetrating through a frame and encapsulant, allowing for vertical electrical connection and improved signal path, while also using insulating material to secure the through-via and control warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are integrated in a compact package, then the quantity of chips per package is improved, but the package thickness increases and warpage control becomes difficult
Solution Approach 1:
The patent transitions from horizontal chip arrangement to vertical stacking by introducing through-vias that penetrate the encapsulant and connect redistribution layers across multiple package structures. This dimensional change allows multiple chips to be integrated in the vertical direction without increasing package footprint, effectively resolving the contradiction between chip quantity and package thickness.
Solution Approach 2:
The patent implements nested packaging where one package structure is disposed within or alongside another package structure. The through-via penetrates through the encapsulant to connect the nested package structures, allowing compact vertical integration that reduces overall package thickness while maintaining multiple chip connections.
2Speed
If through-via is used to connect redistribution layers vertically, then signal transmission speed is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms the through-via and fills it with conductive material before finalizing the package assembly. This preliminary action allows the electrical connection path to be established early in the manufacturing process, simplifying subsequent steps and enabling the speed benefits of vertical connections without proportionally increasing overall manufacturing complexity.
3Length of stationary object
If package thickness is reduced for compact size, then miniaturization is improved, but warpage control becomes more difficult
Solution Approach 1:
The patent employs an encapsulant material with specific mechanical properties that provides structural support and warpage control in the thinned package. The encapsulant acts as a composite structure that maintains package integrity and stability despite reduced thickness, allowing miniaturization without sacrificing warpage control.
Data Source
AI summary
A method includes forming a first package structure including a first connection member including a first redistribution layer, a first frame having a first through-portion, a first semiconductor chip having a connection pad electrically connected to the first redistribution layer, and a first encapsulant covering a portion of each of the first frame and the first semiconductor chip, forming a second package structure including a second connection member including a second redistribution layer, a second semiconductor chip having a second connection pad, and a second encapsulant covering a portion of the second semiconductor chip, forming a first through-via, the first through-via electrically connecting to the second redistribution layer, and laminating the first package structure on the second package structure. After the laminating, the first through-via penetrates through the first frame, the first encapsulant, and a portion of the first connection member, and is electrically connected to the first redistribution layer.