Stacked Semiconductor Package with Through-Via Die Interconnection
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in efficiently integrating multiple semiconductor dies and reducing signal loss through complex electrical pathways, particularly in wafer-level packaging processes.
Innovation Solution
The method involves forming a redistribution circuit structure on a carrier with through vias and semiconductor dies, followed by hybrid bonding and encapsulation, and then forming additional redistribution layers and conductive elements to create a short electrical path between dies, allowing for efficient electrical connection and reduced signal loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex electrical pathways are used to connect multiple semiconductor dies, then electrical connection is achieved, but signal loss increases
Solution Approach 1:
The patent transitions from planar electrical connections to three-dimensional vertical connections through stacked semiconductor dies. Through-vias enable electrical pathways to extend in the vertical dimension, creating direct short connections between dies that eliminate complex lateral routing and reduce signal loss.
Solution Approach 2:
The patent divides the electrical connection system into discrete through-via structures that segment the electrical pathway into manageable vertical segments. Each through-via acts as an independent connection element, allowing optimized electrical pathways through the stacked architecture.
2Adaptability or versatility
If multiple semiconductor dies are integrated in wafer-level packaging, then device functionality is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming through-vias and electrical connection structures on semiconductor wafers before die separation. This preliminary preparation enables subsequent stacking and bonding processes to proceed more efficiently, reducing overall manufacturing complexity despite multiple dies being integrated.
Solution Approach 2:
The patent creates universal through-via structures that serve multiple functions: electrical connection, mechanical alignment, and structural support. This multi-functionality reduces the need for additional specialized components and simplifies the manufacturing process for integrating multiple dies.
3Productivity
If through vias and redistribution layers are formed, then electrical connection efficiency is improved, but manufacturing steps increase
Solution Approach 1:
The patent merges the formation of through-vias and redistribution layers into an integrated manufacturing process. Multiple electrical connection functions are combined into unified structural elements that are formed in coordinated steps, improving electrical connection efficiency while managing manufacturing complexity through process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient electrical communication between semiconductor dies, reducing signal loss and improving the integration of multiple dies within semiconductor packages, enhancing the performance and yield of wafer-level packaging processes.
Implementation Method 1
the carrier and the semiconductor dies are hybrid bonded to one another
Data Source
AI summary
A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.