Stacked Semiconductor Package Structure to Eliminate Triple-Point Stress
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high performance, large capacity, miniaturization, and reliability due to issues with stress concentration at triple points, which affect the integrity and functionality of stacked semiconductor chips.
Innovation Solution
A semiconductor package design that includes a base structure, multiple semiconductor chips stacked with adhesive layers and connecting structures, covered by a molding layer with an interposition portion that alleviates stress concentration by eliminating triple points, enhancing reliability through the use of a polymer-based molding layer with ceramic fillers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a molding layer is formed to cover stacked semiconductor chips, then the chips are protected and structurally supported, but stress concentration occurs at triple points where the molding layer, adhesive layer, and semiconductor chip intersect
Solution Approach 1:
The patent removes the harmful triple point intersections by extracting the molding layer from directly contacting the semiconductor chips at corner regions. Instead, the molding layer is positioned to contact only the adhesive layer, eliminating the stress concentration points where three materials previously met.
Solution Approach 2:
The adhesive layer serves as an intermediary between the molding layer and semiconductor chip, preventing direct contact at corner regions. This intermediary positioning reduces stress transmission to the chip corners, eliminating the harmful triple point stress concentration.
2Quantity of substance
If multiple semiconductor chips are stacked to achieve high capacity and miniaturization, then device functionality is enhanced, but stress concentration at triple points compromises reliability
Solution Approach 1:
The patent extracts the molding layer from direct contact with semiconductor chip corners in stacked configurations, removing the source of stress concentration that would compromise reliability while maintaining the high-capacity stacked architecture.
Solution Approach 2:
The patent applies different contact qualities at different locations: the molding layer contacts the adhesive layer at corner regions to prevent stress concentration, while maintaining coverage and protection over the central regions of the stacked chips.
3Strength
If the molding layer directly contacts the semiconductor chip at triple points, then structural support is provided, but stress concentration reduces package durability
Solution Approach 1:
The patent extracts the molding layer from direct contact with semiconductor chip corners, removing the stress concentration mechanism that would reduce package durability over time, while maintaining adequate structural support through adhesive layer contact.
Solution Approach 2:
The adhesive layer acts as a cushioning layer between the molding layer and semiconductor chip corners, absorbing and distributing stresses before they can concentrate at the chip corners, thereby extending package durability.
Data Source
AI summary
A semiconductor package is disclosed. The semiconductor package includes a base structure, a first semiconductor chip over the base structure, a second semiconductor chip over the first semiconductor chip, an adhesive layer between the first semiconductor chip and the second semiconductor chip, and a molding layer covering the first semiconductor chip, the second semiconductor chip and the adhesive layer, and including an interposition portion interposed between the base structure and the first semiconductor chip.