Stacked Semiconductor Package Layout for Low-Height TSV Interconnects
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Solution Overview
Problem
The challenge is to create a semiconductor package with reduced vertical height and improved connection reliability, as existing technologies face difficulties in miniaturization and maintaining consistent inter-chip connections due to variations in redistribution line thickness and positioning.
Innovation Solution
The semiconductor package design includes a lower semiconductor chip with a TSV structure connected to a conductive line in the BEOL layer, a redistribution line impregnated in a passivation layer, and an inter-chip connection structure using intermediate insulating layers to connect the upper and lower BEOL layers, which reduces the overall package height and enhances connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the vertical height of the semiconductor package is reduced for miniaturization, then the package size is decreased, but the connection reliability between chips deteriorates due to variations in redistribution line thickness and positioning
Solution Approach 1:
The patent introduces a redistribution structure with intermediate insulating layers and via holes as mediators between the first and second semiconductor chips. The intermediate insulating layers (330, 360) and via holes (325, 345) serve as intermediary connection elements that enable reliable electrical connection between chips while accommodating variations in redistribution line thickness and positioning, thus resolving the contradiction between reduced package height and maintained connection reliability
Solution Approach 2:
The patent employs a nested structure where the redistribution line (320, 340) is impregnated within the intermediate insulating layers (330, 360), and via holes (325, 345) are formed through these layers to connect different levels. This nesting approach allows compact vertical integration while maintaining connection reliability through the hierarchical arrangement of conductive and insulating elements
2Reliability
If multiple redistribution lines and insulating layers are added to improve connection reliability, then the connection stability is enhanced, but the device complexity increases
Solution Approach 1:
The patent merges the redistribution function with the insulating function by integrating redistribution lines (320, 340) within intermediate insulating layers (330, 360). This consolidation reduces the need for separate redistribution structures and simplifies the overall device architecture while maintaining connection reliability through the combined structure
3Length of stationary object
If the redistribution line is impregnated in the passivation layer to reduce height, then the vertical space is optimized, but the manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned via hole formation where via holes (325, 345) are automatically positioned based on the redistribution line (320, 340) pattern within the intermediate insulating layers (330, 360). This self-service approach reduces the need for high-precision external alignment processes, allowing the redistribution line to be impregnated in the passivation layer for height reduction while managing manufacturing precision requirements
Data Source
AI summary
A semiconductor package includes a package-bottom redistribution structure at a lower side of a package and including a conductive line, an upper semiconductor chip at an upper side of the package, an upper back end of line (BEOL) layer, at a lower side of the upper semiconductor chip, and including a conductive line, a lower semiconductor chip below the upper semiconductor chip, where a horizontal width of the lower semiconductor chip is less than a horizontal width of the upper semiconductor chip, and where the upper semiconductor chip overlaps at least a portion of the lower semiconductor chip, a lower BEOL layer at a lower side of the lower semiconductor chip and including a conductive line, a passivation layer on an upper surface of the lower semiconductor chip, and a through silicon via (TSV) structure penetrating the passivation layer and the lower semiconductor chip.