Stacked Semiconductor Package TSV Landing on Bonding Pads

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The existing via last scheme in semiconductor package manufacturing often results in copper (Cu) punch-through due to total thickness variation (TTV) during the chemical mechanical planarization (CMP) process, as through silicon via (TSV) is formed on metal wiring rather than the bonding pad of the insulation interlayer.

Innovation Solution

The TSV is formed to land directly on the bonding pad in the outermost insulation layer, preventing Cu punch-through by ensuring it contacts the bonding pad rather than the metal wiring, thereby maintaining a stable thickness and preventing copper penetration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If TSV is formed after forming insulation interlayer using via last scheme, then manufacturing flexibility is improved, but TSV may land on metal wiring causing Cu punch-through due to TTV in CMP process

Engineering Contradiction:

Improvemanufacturing flexibilityVSAvoidTSV positioning accuracy

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a thickness compensation layer in the insulation interlayer before forming the TSV. This compensation layer is specifically designed to offset the TTV that occurs during the subsequent CMP process, ensuring that the TSV landing position remains accurate and prevents Cu punch-through while maintaining the via last manufacturing flexibility

Inventive Principle:

Principle #10Preliminary action

2Shape

If CMP process is performed to planarize the surface, then surface flatness is improved, but TTV occurs causing TSV to land on metal wiring instead of bonding pad

Engineering Contradiction:

Improvesurface flatnessVSAvoidTSV landing position

Core Design Contradiction:

ShapeVSManufacturing precision

Solution Approach 1:

The thickness compensation layer is formed in advance in the insulation interlayer to preemptively counteract the thickness variation that will occur during CMP. This preliminary structural preparation ensures that even after CMP planarization, the TSV will land on the bonding pad rather than on metal wiring

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The compensation layer acts as a cushioning structure that absorbs and compensates for the thickness variation caused by CMP. By placing this compensatory layer beforehand, the patent creates a buffer that prevents the TSV positioning error that would otherwise result from CMP-induced TTV

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11804472B2Semiconductor device, semiconductor package and method of manufacturing the same

Publication Date: 2023.10.31 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.