Stacked Semiconductor Package Layout for Reduced TSV Pitch
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Solution Overview
Problem
The challenge in high bandwidth memory (HBM) devices is the difficulty in reducing the pitch of through silicon vias (TSVs) due to the space occupied by I/O driver circuits, limiting the number of input/output channels.
Innovation Solution
A semiconductor package design with alternating groups of through electrodes on each chip, where only one group is connected to I/O circuitry, allowing for a staggered I/O pattern and reducing pitch between TSVs, thereby increasing the number of TSVs and implementing a broadband interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of through silicon vias is reduced to increase the number of I/O channels, then the data transmission capacity is improved, but the space occupied by I/O driver circuits makes it difficult to reduce the pitch
Solution Approach 1:
The through electrodes are divided into two distinct groups: a first group electrically connected to I/O circuitry and a second group not connected to I/O circuitry. This segmentation allows the I/O driver circuits to be positioned only around the first group of through electrodes, freeing up space and enabling reduced pitch between through electrodes overall, thereby increasing the total number of I/O channels without proportionally increasing the space occupied by driver circuits.
2Length of moving object
If alternating groups of through electrodes are used with staggered I/O pattern, then the pitch between TSVs is reduced, but the device complexity increases
Solution Approach 1:
The patent employs an asymmetric arrangement where alternating groups of through electrodes (first and second groups) have different electrical connection configurations. The first group connects to I/O circuitry while the second group does not, creating a staggered I/O pattern. This asymmetric design enables reduced pitch between through electrodes by eliminating the need for I/O driver circuits around every through electrode, thereby reducing the effective pitch requirement while managing device complexity through functional differentiation.
Data Source
AI summary
A semiconductor package includes a semiconductor package includes first, second, third and fourth semiconductor chips sequentially stacked on one another. Each of the first, second, third and fourth semiconductor chips includes a first group of bonding pads and a second group of bonding pads alternately arranged in a first direction and input/output (I/O) circuitry selectively connected to the first group of bonding pads respectively. Each of the first, second and third semiconductor chips includes a first group of through electrodes electrically connected to the first group of bonding pads and a second group of through electrodes electrically connected to the second group of bonding pads.