Stacked Semiconductor Package Groove Structure for Underfill Containment
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Solution Overview
Problem
In multi-chip packages, the overflow of underfill material during flip chip bonding reduces the degree of freedom for chip arrangement and necessitates additional dam structures, limiting the design flexibility.
Innovation Solution
A semiconductor package design featuring a receiving groove in the package substrate, where a first semiconductor chip is partially inserted, is used with an underfill member that fills the groove and covers the chip, allowing sequential stacking of multiple chips without overflow, and a molding member encapsulates the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dam structure is added to prevent underfill overflow, then underfill overflow is prevented, but the degree of freedom for chip arrangement is reduced
Solution Approach 1:
The receiving groove is formed in advance on the package substrate before chip mounting. This preliminary structural preparation provides built-in containment for the underfill material, eliminating the need for additional dam structures while maintaining chip arrangement flexibility. The groove is positioned and sized to match the specific chip layout requirements.
Solution Approach 2:
The receiving groove serves multiple functions simultaneously: it contains the underfill material to prevent overflow, provides a recessed mounting area for the chip, and eliminates the need for separate dam structures. This multi-functional design maintains structural simplicity while achieving both overflow prevention and arrangement flexibility.
2Area of stationary object
If the package size is reduced, then miniaturization is achieved, but the space for chip arrangement and underfill containment is limited
Solution Approach 1:
The receiving groove utilizes the vertical dimension by extending downward from the surface of the package substrate. This vertical containment allows the underfill material to be confined in the depth direction rather than requiring lateral expansion, enabling miniaturization of the package footprint while maintaining adequate space for chip arrangement and underfill containment.
Solution Approach 2:
The chip is positioned within the receiving groove, nesting the chip mounting area within the groove structure. This nested arrangement optimizes space utilization by having the chip and underfill material occupy the recessed volume of the groove, thereby reducing the overall package footprint while maintaining functional requirements.
Data Source
AI summary
A semiconductor package includes a package substrate having an upper surface, a lower surface opposite to the upper surface, and a receiving groove that extends from the upper surface, toward the lower surface, by a predetermined depth; a first semiconductor chip in the receiving groove and protruding from the upper surface of the package substrate to have a predetermined height from the upper surface of the package substrate; an underfill member in the receiving groove and between the first semiconductor chip and an inner surface of the receiving groove; a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip; and a molding member on the package substrate and covering the first semiconductor chip and the plurality of second semiconductor chips.