Stacked Semiconductor Package Layout for Heat Radiation and Underfill Flow
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Solution Overview
Problem
Stacked multi-chip semiconductor packages face challenges with heat radiation efficiency and under-fill process defects due to increased chip stacking, leading to chip degradation and structural instability.
Innovation Solution
The semiconductor package design includes a first die with a signal region and a dummy region, featuring vias, pads, and connection terminals, along with a second die stacked on the first die, utilizing a substrate with under-fill and a molding layer, where the dummy pads and bumps facilitate efficient thermal radiation and under-fill flow, preventing process defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the number of stacked chips is increased to improve performance and reduce size, then the compactness and integration are improved, but the thermal radiation efficiency deteriorates causing chip degradation
Solution Approach 1:
The patent segments the package structure by introducing a dedicated heat dissipation layer separate from the signal processing layers. This layer is positioned between the stacked chips and the external environment, allowing thermal management to be handled independently from the computational functions, thereby maintaining compact size while improving thermal radiation efficiency.
Solution Approach 2:
The patent transitions from planar heat dissipation to three-dimensional thermal management by utilizing the vertical space within the stacked package. The heat dissipation structures extend in the Z-direction (stacking direction) and incorporate lateral surfaces that radiate heat outward, effectively using the third dimension to increase thermal radiation area without expanding the package footprint.
2Productivity
If the number of stacked chips is increased to improve integration, then the device density is improved, but the under-fill process creates blockages causing manufacturing defects
Solution Approach 1:
The patent segments the inter-chip space by introducing a heat dissipation layer with specific structural features that create controlled pathways. These pathways are intentionally designed to guide under-fill material flow, preventing random blockages while maintaining the high-density stacked configuration. The segmentation of space into flow channels and structural support zones resolves the conflict between density and manufacturability.
3Volume of moving object
If more chips are stacked to reduce package size, then the compactness is improved, but the structural stability deteriorates
Solution Approach 1:
The heat dissipation layer serves multiple functions simultaneously: it provides thermal management, acts as a structural support framework, and guides under-fill material flow. This multi-functionality allows a single structural element to maintain package stability while enabling high-density stacking, resolving the contradiction between compactness and structural integrity.
Solution Approach 2:
The patent applies local quality enhancement by strategically positioning heat dissipation structures with lateral surfaces at specific locations within the stack. These localized structures provide targeted structural support where needed most, particularly at interfaces between stacked chips, thereby maintaining overall package stability without requiring uniform reinforcement throughout the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances thermal radiation efficiency and structural stability while preventing under-fill obstruction, reducing the occurrence of defects and improving the overall performance of the semiconductor package.
Implementation Method 1
an increase in the number of stacked chips may increase the amount of circuit chips in the package and the gap fill between the chips, and may also induce degradation of the chips. For example, a semiconductor package with a relatively high number of stacked chips might not be able to radiate and/or dispose of heat efficiently
Data Source
AI summary
Disclosed is a semiconductor package with increased thermal radiation efficiency, which includes: a first die having signal and dummy regions and including first vias in the signal region, a second die on the first die and including second vias in the signal region, first die pads on a top surface of the first die and coupled to the first vias, first connection terminals on the first die pads which couple the second vias to the first vias, second die pads in the dummy region and on the top surface of the first die, and second connection terminals on the second die pads and electrically insulated from the first vias and the second vias. Each of the second die pads has a rectangular planar shape whose major axis is provided along a direction that leads away from the signal region.