Stacked Semiconductor Package With Upper Lead Heat Dissipation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Semiconductor packages with stacked dies face issues such as premature die failure, difficulty in designing electrical ground paths, heat dissipation, adhesive moisture absorption, and thermal mismatch, leading to reduced reliability and increased manufacturing costs.

Innovation Solution

The semiconductor package design incorporates a leadframe with an upper lead and an elevated die paddle assembly to support dies, using a ball grid array for connectivity and minimizing adhesive material, along with a method of manufacturing that includes wire bonding and encapsulation to enhance structural support and reduce cracking risks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple dies are stacked in a semiconductor package, then circuit density and functionality are improved, but heat dissipation becomes more difficult

Engineering Contradiction:
Improvecircuit densityVSAvoidheat dissipation
Core Design Contradiction:
Quantity of substanceVSTemperature

Solution Approach 1:

The patent transitions from lateral heat dissipation in traditional packages to vertical heat dissipation through the stacked die architecture. Heat can escape through the top surface of the uppermost die and through the substrate, utilizing the third dimension (vertical space) to improve thermal management while maintaining high circuit density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the heat dissipation function across multiple thermal pathways: through-substrate heat sinks, top-surface heat sinks for each die, and lateral heat spreading. This segmentation of thermal management functions allows efficient heat removal from multiple sources simultaneously.

Inventive Principle:
Principle #1Segmentation

2Strength

If adhesive material is used to position stacked dies, then mechanical support is improved, but moisture absorption increases reducing reliability

Engineering Contradiction:
Improvemechanical supportVSAvoidmoisture absorption
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent uses thin film adhesive layers to bond dies to heat sinks and to each other. These minimal-thickness adhesive films provide necessary mechanical support while minimizing the volume of moisture-absorbing material, thereby maintaining reliability.

Inventive Principle:
Principle #30Flexible shells and thin films

Solution Approach 2:

The patent employs thermocompression bonding and other permanent bonding techniques that eliminate or minimize the need for continuous adhesive materials, replacing them with durable mechanical and metallurgical bonds that do not absorb moisture.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Adaptability or versatility

If an upper die overhangs the next lower die, then layout flexibility is improved, but die cracking occurs due to lack of vertical support

Engineering Contradiction:
Improvelayout flexibilityVSAvoiddie cracking
Core Design Contradiction:
Adaptability or versatilityVSStrength

Solution Approach 1:

The patent introduces intermediate support structures, including extended substrate areas, temporary support frames, and reinforced bonding layers, that provide vertical support to overhanging dies during the wire-bonding process. These intermediaries allow layout flexibility while preventing die cracking.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements preventive support mechanisms before wire-bonding begins, such as temporary support structures and reinforced bonding adhesives, that cushion and protect overhanging dies from cracking during subsequent manufacturing processes.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

4Quantity of substance

If more dies are placed in a semiconductor package, then functionality is improved, but the flow of molding compound is obstructed

Engineering Contradiction:
Improvenumber of diesVSAvoidmolding compound flow
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent arranges dies in a vertical stack rather than a lateral array, changing the packaging from two-dimensional to three-dimensional. This vertical arrangement allows molding compound to flow more easily through the package structure without being blocked by multiple dies occupying the same horizontal plane.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces die cracking, improves heat dissipation, minimizes adhesive moisture absorption, and increases reliability, allowing for more dies in a package while maintaining cost-effectiveness and efficiency in manufacturing.

Implementation Method 1

the head of a wire-bonding apparatus applies a downward pressure on a conductive wire held in contact with a wire-bonding pad on the die to weld, or bond, the wire to the bonding pad on the die

Methodology Applied
Scientific EffectThermal compression:

Implementation Method 2

thermal compression or ultrasonic wire-bonding techniques

Methodology Applied
Scientific EffectUltrasonic wire-bonding: Ultrasonic Vibration

Data Source

PatentUS7667308B2Leaded stacked packages having integrated upper lead
Publication Date: 2010.02.23 STATS CHIPPAC LTD
  • US7667308B2 patent drawing
  • US7667308B2 patent drawing
  • US7667308B2 patent drawing

AI summary

A semiconductor package includes a leadframe. An upper lead is disposed above the leadframe. A first die is attached to a lower surface of the upper lead to provide electrical conductivity from the first die to the upper lead. A second die is attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having an upper lead, lower lead, and an elevated die paddle. A first die, attached to a plurality of dies in a wafer form, is attached to a second die. The first die is singulated from the plurality of dies. The first and second dies are attached to the elevated die paddle structure. The first die is wire bonded to the lower lead. An encapsulant is formed over the first and second dies. The elevated die paddle is removed to expose a surface of the upper lead and second die.