Stacked Semiconductor Package with Vertical Interconnect Frame
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Solution Overview
Problem
Current semiconductor package technologies face challenges in achieving high performance while minimizing package size, particularly in package-on-package configurations, due to limitations in connecting multiple semiconductor chips efficiently and securely.
Innovation Solution
The proposed semiconductor package design includes a redistribution substrate with a frame having through-holes for accommodating semiconductor chips, vertical connection conductors, and encapsulants, along with conductive wires and redistribution structures to connect multiple chips in a stacked configuration, enhancing electrical connectivity and rigidity while allowing for varying chip dimensions and positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor chips are connected in a stacked configuration, then electrical connectivity and performance are improved, but package size and complexity increase
Solution Approach 1:
The patent implements package-on-package stacking where multiple semiconductor packages are vertically integrated. The first package contains a first semiconductor chip, and the second package contains a second semiconductor chip positioned above it. Through-holes penetrate through the packages to enable electrical connections between chips in different packages, creating a nested three-dimensional structure that improves connectivity while managing complexity through systematic design.
Solution Approach 2:
The patent transitions from traditional planar chip arrangements to a three-dimensional stacked configuration. By utilizing the vertical dimension with multiple packages stacked above each other and connecting them through through-holes, the design achieves enhanced electrical connectivity and performance without proportionally increasing the footprint area, thus managing overall package complexity.
2Reliability
If chip dimensions and positions are varied to optimize performance, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs redistribution structures within each package that are specifically designed to accommodate and correct for variations in chip dimensions and positions. These redistribution structures locally adjust the electrical connection geometry, allowing chips with different sizes and positions to be properly interconnected without requiring extremely tight manufacturing tolerances across the entire package assembly.
3Reliability
If encapsulation is used to protect chips, then reliability is improved, but access to connection pads becomes difficult
Solution Approach 1:
The patent divides the encapsulation into functional regions. The encapsulant material protects the chips and internal structures, but specific areas are left exposed or accessible through openings to allow connection pads to remain accessible for external connections. This segmentation of the encapsulation structure maintains protection while preserving necessary access points.
Data Source
AI summary
A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.