Electronic device package and method for manufacturing the same
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Solution Overview
Problem
Chip-on-chip (CoC) packages face signal integrity issues and high impedance due to long transmission paths and high resistance of bond wires, limiting high-speed data rates such as 100 Gbit/s, 400 Gbit/s, or 1.6 Tbit/s in high-frequency applications, especially when integrating electronic ICs and photonic ICs.
Innovation Solution
The electronic device package employs a circuit layer with first and second semiconductor dies, where conductive structures with lower resistance than bond wires are used to connect the dies and the circuit layer, forming a fan-out package-on-package structure with redistribution trace layers and encapsulation to optimize signal transmission paths for high-speed data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bond wires are used to connect stacked electronic components in CoC package, then electrical connection between components is achieved, but high resistance and long transmission path cause signal integrity degradation and prevent high speed data rate realization
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical interconnection using conductive structures such as conductive pillars and through-substrate vias. This dimensional change allows signals to travel through the substrate vertically rather than along extended wire paths, dramatically reducing transmission path length and improving signal integrity for high-speed applications.
Solution Approach 2:
The patent replaces the mechanical wire bonding process with a fabricated conductive structure system. Instead of using flexible bond wires that require manual or automated wire bonding equipment, the invention uses rigid conductive pillars and via structures that are formed through semiconductor manufacturing processes, eliminating the high resistance and inductance associated with wire bonds.
2Productivity
If extended transmission path is used in CoC package, then connection between components is established, but high impedance prevents high speed data rate such as 100 Gbit/s, 400 Gbit/s, or 1.6 Tbit/s from realization
Solution Approach 1:
The patent changes the physical parameters of the interconnection system by replacing bond wires with conductive structures that have lower resistance and controlled impedance characteristics. The conductive pillars and via structures are designed with specific dimensions and materials to optimize electrical parameters, enabling support for high-speed data rates of 100 Gbit/s, 400 Gbit/s, and 1.6 Tbit/s while maintaining proper impedance control throughout the signal path.
3Reliability
If conductive structures with lower resistance are used to replace bond wires, then signal transmission path length and impedance are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of conductive pillars, via structures, and redistribution layers into an integrated manufacturing process. Multiple interconnection functions are combined into unified fabrication steps using standard semiconductor manufacturing techniques, reducing the overall manufacturing complexity despite the advanced functionality provided by the conductive structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces signal transmission path length and impedance, enabling high-speed signal transmission beyond 400 Gbit/s by using conductive structures like copper pillars, thereby alleviating signal integrity issues and allowing for efficient data transfer in high-frequency applications.
Implementation Method 1
The first conductive structures are disposed between a first region of the second semiconductor die and the second semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die
Implementation Method 2
The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die
Data Source
AI summary
An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.