Stacked Semiconductor Package with Vertical Posts for Dense Wiring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in implementing high-density wiring due to technological limitations and thickness constraints, particularly in mobile devices, which hinder the development of thinner and smaller electronic products with higher capacity.
Innovation Solution
A semiconductor package design featuring vertically stacked lower and upper chip structures with insulating layers and vertical connection conductors that are spaced apart and connected to posts, allowing for reduced thickness and increased wiring density without direct wire bonding, using posts for electrical paths and a redistribution structure for cost-effective miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional wire bonding is used for electrical connections, then the process is simple and cost-effective, but the wiring density is limited and the package thickness cannot be reduced
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical connections using conductive posts extending through multiple chip layers. This dimensional change enables high-density wiring by utilizing the vertical axis for electrical connections, allowing multiple connection points within a compact footprint area.
Solution Approach 2:
The patent implements nested structures where conductive posts are embedded within insulating layers, which are themselves embedded within molding compounds. Multiple chip structures are stacked vertically with connection posts nested through intermediate layers, creating a compact nested architecture that achieves high wiring density without increasing package footprint.
2Quantity of substance
If multiple chips are stacked to increase capacity, then the functional capacity increases, but the package thickness increases which conflicts with mobile device requirements
Solution Approach 1:
The patent employs thin insulating layers and compact molding compounds that encapsulate multiple chip structures vertically. These thin film structures provide electrical isolation and mechanical protection while minimizing the vertical space occupied, enabling high-capacity multi-chip stacking without proportionally increasing package thickness.
Solution Approach 2:
The patent merges multiple functional elements into integrated vertical structures: conductive posts serve both as mechanical support and electrical interconnects, insulating layers provide both electrical isolation and structural spacing, and molding compounds encapsulate multiple chips while providing environmental protection. This merging reduces overall package thickness compared to separate discrete components.
3Manufacturing precision
If high-density wiring is implemented using conventional methods, then wiring capacity increases, but the process cost increases and manufacturing becomes more difficult
Solution Approach 1:
The patent forms conductive posts and insulating layers during the chip fabrication process itself, before final packaging. This preliminary action integrates the interconnect structure creation with standard semiconductor manufacturing steps, avoiding the need for separate, complex post-packaging wiring operations and reducing overall manufacturing difficulty.
Solution Approach 2:
The conductive posts are formed using standard semiconductor deposition and patterning techniques that are already part of the chip manufacturing process. The insulating layers are deposited using conventional thin-film techniques. This self-service approach leverages existing manufacturing capabilities to achieve high-density wiring without introducing new, complex process steps.
Data Source
AI summary
Provided is a semiconductor package including a lower semiconductor chip structure including: a plurality of lower dies stacked in a vertical direction; a lower post extending in the vertical direction from an upper surface of a lower die among the plurality of lower dies; and an insulating layer surrounding the lower post; an upper semiconductor chip structure above the lower semiconductor chip structure; and a vertical connection conductor on the lower semiconductor chip structure, wherein the vertical connection conductor is spaced apart from the upper semiconductor chip structure in a horizontal direction and is connected to the lower post.