Stacked Electronic Package With Vertical Vias for Shorter Signal Paths
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Solution Overview
Problem
Conventional semiconductor packages with side-by-side chip integration result in long electrical signal transmission distances, leading to poor electrical performance that fails to meet performance requirements.
Innovation Solution
An electronic package design featuring stacked electronic modules with conductive vias and circuit structures, connected via conductive pillars and routing structures, reducing signal transmission distance and enhancing electrical performance through vertical circuit conduction paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are integrated in a side by side manner, then the packaging structure is simple, but the electrical signal transmission distance becomes too long resulting in poor electrical performance
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side chip arrangement to a three-dimensional stacked configuration. Multiple semiconductor chips are vertically stacked and connected through conductive pillars, transforming the layout from lateral to vertical space utilization. This dimensional change dramatically reduces the electrical signal transmission distance between chips while maintaining a compact packaging footprint, thereby resolving the contradiction between electrical performance and packaging simplicity.
2Length of moving object
If semiconductor chips are integrated in a side by side manner, then the manufacturing process is simple, but the transmission distance of electrical signals is too long
Solution Approach 1:
The patent divides the single packaging structure into multiple stacked layers, with each layer containing semiconductor chips and associated conductive structures. The conductive pillars are segmented to connect corresponding pads between adjacent chips vertically. This segmentation approach enables shorter signal transmission paths within each layer while the overall manufacturing process remains modular and manageable, thus reducing signal transmission distance without excessively complicating the manufacturing process.
3Reliability
If vertical stacking structure is implemented, then the electrical signal transmission distance is reduced, but the packaging layer experiences warpage
Solution Approach 1:
The patent introduces a compensation layer with locally differentiated properties to counteract the warpage caused by vertical stacking. This compensation layer is positioned at specific locations within the packaging structure and has tailored material characteristics (such as different thermal expansion coefficients or mechanical properties) that locally compensate for the stress and deformation induced by the stacked chips. This local quality adjustment maintains packaging layer stability while preserving the electrical performance benefits of the vertical stacking configuration.
Data Source
AI summary
An electronic package is provided, in which a stacking component and a plurality of conductive pillars are embedded in a packaging layer, and a routing structure is formed on the packaging layer, where the stacking component is formed by stacking a first electronic module and a second electronic module on each other, and a plurality of first conductive vias and a plurality of second conductive vias are served as the electrical connection paths between the first electronic module and the second electronic module, such that the transmission distance of electrical signals between a first electronic element in the first electronic module and a second electronic element in the second electronic module can be reduced.