Stacked Semiconductor Package With Vertical Wire Interconnects
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Solution Overview
Problem
The high integration of semiconductor devices leads to increased thickness and complexity in manufacturing due to wire bonding of stacked semiconductor chips, limiting their capacity and efficiency.
Innovation Solution
A semiconductor package design that includes a package substrate with vertically stacked semiconductor chips connected via vertical wires and chip connection members, reducing thickness and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to provide electrical input/output between stacked semiconductor chips and package substrate, then electrical connection is achieved, but package thickness increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from horizontal wire bonding to vertical wire configuration. The wire extends vertically from the package substrate through the stacked semiconductor chips, utilizing the vertical dimension for electrical connection. This dimensional change reduces the horizontal space required for bonding and simplifies the manufacturing process while maintaining reliable electrical connection between chips and substrate.
2Reliability
If wire bonding is used to connect stacked semiconductor chips, then electrical connection is established, but manufacturing process complexity increases
Solution Approach 1:
The invention changes the wire configuration from horizontal bonding to vertical extension. The wire is positioned to extend vertically from the package substrate, passing through or alongside the stacked semiconductor chips. This vertical arrangement simplifies the bonding process by reducing the number of bonding steps and aligning the wire direction with the stacking direction, thereby reducing manufacturing complexity while ensuring reliable electrical connection.
3Quantity of substance
If multiple semiconductor chips are stacked to achieve high capacity, then device capacity increases, but package thickness increases
Solution Approach 1:
The patent employs a nested structure where semiconductor chips are stacked vertically one on top of another, with each chip containing functional elements that contribute to overall device capacity. The vertical wire configuration penetrates or runs alongside this nested stack, providing electrical connection through all layers. This nesting approach maximizes capacity within a compact vertical footprint, reducing the horizontal space required while maintaining high device capacity.
Data Source
AI summary
A semiconductor package includes a package substrate, a first semiconductor chip disposed on the package substrate, and a second semiconductor chip stacked in a step structure on the first semiconductor chip. A first chip pad is disposed on a first front surface of the first semiconductor chip, and the first chip pad is connected to a first upper surface connection pad disposed on the package substrate. A second chip pad is disposed on a second front surface of the second semiconductor chip, and the second chip pad is connected to a second upper surface connection pad disposed on the package substrate by a vertical wire.