Stacked Semiconductor Package With Vertical Wire Bonding and EMI Shielding
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving miniaturization, weight reduction, and cost-effectiveness while maintaining electrical connectivity and shielding from electromagnetic interference, particularly in stacked semiconductor chip configurations.
Innovation Solution
A semiconductor package design featuring a redistribution layer with vertical wires connecting stacked semiconductor chips through bonding surfaces within molding layers, along with a metal layer for electromagnetic shielding, and a manufacturing method that includes offset stacking and selective grinding of molding layers to optimize wire connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are stacked to achieve miniaturization, then integration density is improved, but wire length increases and electrical short risk worsens
Solution Approach 1:
The patent transitions from planar wire routing to three-dimensional vertical wire routing through stacked chip architecture. Wires are routed vertically through molding layers between chips at different height levels, enabling compact packaging while maintaining controlled wire lengths through precise vertical positioning and offset stacking techniques.
2Volume of moving object
If multiple chips are stacked closely, then integration density is improved, but electromagnetic interference increases
Solution Approach 1:
Molding layers serve as intermediary shielding structures between stacked semiconductor chips. These molding layers are positioned to physically separate chips while providing electromagnetic shielding, thus reducing interference between adjacent chips in the stack without compromising integration density.
3Reliability
If complex wire routing is used to connect stacked chips, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The wire routing is segmented into discrete portions embedded in separate molding layers. Each molding layer contains specific wire segments that connect to corresponding chips, allowing independent fabrication and assembly of stacked modules. This segmentation simplifies manufacturing by enabling modular production and reducing the complexity of routing entire wire paths through multiple layers simultaneously.
4Reliability
If wire bonding is performed at multiple levels, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
Wire bonding is performed preliminarily within each molding layer before stacking, rather than attempting to bond wires across multiple layers simultaneously. Each molding layer is prepared with its wire bonds in advance, then layers are stacked and aligned. This preliminary bonding approach reduces precision requirements by breaking down complex multi-level bonding into simpler, independent single-layer bonding operations.
Data Source
AI summary
A semiconductor package includes: a redistribution layer; a lower semiconductor chip disposed on the redistribution layer; an upper semiconductor chip stacked on the lower semiconductor chip; a lower molding layer covering the lower semiconductor chip; an upper molding layer covering the upper semiconductor chip; a first wire connecting the lower semiconductor chip and the redistribution layer to each other in a vertical direction; and a second wire connecting the upper semiconductor chip and the redistribution layer to each other in the vertical direction, wherein the second wire includes a first portion, a second portion, and a bonding surface, wherein the first portion is disposed in the lower molding layer, wherein the second portion is disposed in the upper molding layer, and wherein the first portion of the second wire and the second portion of the second wire are bonded to each other at the bonding surface.