Stacked Semiconductor Package Layout to Prevent Via-Pad Delamination
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving structural stability and improved electrical characteristics, particularly due to stress concentrations in interconnection lines and potential delamination issues between pads and vias.
Innovation Solution
The semiconductor package design includes a stack configuration where the first and second semiconductor chips are directly contacted, with pads made of the same material forming a single integral object. The vias are shifted parallel to the substrate, and the pads are horizontally spaced from the vias, allowing for electrical connection through an interconnection layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vias are vertically aligned with pads in stacked semiconductor chips, then electrical connection is simplified, but stress concentrates at the via-pad interface causing delamination
Solution Approach 1:
The patent shifts the via position from vertical alignment with the pad to a horizontal offset configuration. The via is positioned at a first position while the pad is at a second position, creating a horizontal separation that disperses stress away from the via-pad interface. This dimensional change in positioning resolves the stress concentration issue while maintaining electrical connection through the interconnection layer.
Solution Approach 2:
The patent introduces an interconnection layer as an intermediary element between the via and the pad. This interconnection layer provides a separate pathway for electrical connection, allowing the via to connect to the pad through this intermediate structure rather than requiring direct via-pad contact. This mediator reduces stress at the interface while maintaining electrical functionality.
2Ease of manufacture
If pads and vias are directly aligned vertically, then manufacturing process is simpler, but stress concentration causes delamination between pads and vias
Solution Approach 1:
The patent changes the relative positioning from vertical alignment to horizontal offset. The via and pad are positioned at different horizontal locations, which disperses the stress that would otherwise concentrate at the vertical interface. This dimensional repositioning maintains manufacturing feasibility while significantly improving resistance to delamination.
Solution Approach 2:
The patent segments the electrical connection path into separate components: the via, the interconnection layer, and the pad, positioned at different locations. This segmentation allows each component to be optimized independently and reduces the stress concentration that occurs when via and pad are directly aligned, thereby improving reliability without excessive manufacturing complexity.
3Reliability
If vertical stress is concentrated at via-pad interface, then electrical connection is direct, but structural stability deteriorates due to delamination risk
Solution Approach 1:
The patent repositions the via and pad in different horizontal locations rather than vertical alignment. This spatial reconfiguration disperses the vertical stress through the interconnection layer, preventing concentration at a single interface point. The electrical connection remains stable while the interface bonding strength is preserved by eliminating stress concentration.
Solution Approach 2:
The interconnection layer serves as a mediator that distributes the electrical connection function across a larger area and different location. This intermediary structure reduces the stress burden on any single interface, maintaining both electrical connection stability and interface bonding strength by separating the via and pad positions horizontally.
Data Source
AI summary
A semiconductor package may include a first semiconductor chip and a second semiconductor chip below the first semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, a first semiconductor device and a first interconnection layer on a bottom surface of the first semiconductor substrate, a first via penetrating the first semiconductor substrate and electrically connected to the first interconnection layer, and a first pad on a bottom surface of the first interconnection layer. The second semiconductor chip may include a second semiconductor substrate, a second via penetrating the second semiconductor substrate, and a second pad on a top surface of the second semiconductor substrate and electrically connected to the second via. The first and second vias may be shifted from each other in a horizontal direction, and the first via may be horizontally spaced apart from the first pad, when viewed in a plan view.