Stacked Semiconductor Package Through-Hole Molding Against Void Traps
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Solution Overview
Problem
The challenge in semiconductor packaging is the occurrence of void traps during the molding process when multiple semiconductor chips are stacked, leading to defects in the packaging process.
Innovation Solution
The solution involves a semiconductor package design with strategically formed holes in the package substrates that allow for the direct stacking of chips and the use of a mold film to cover and connect the chips, ensuring that voids are discharged during the encapsulation process, thereby improving product reliability and allowing for efficient encapsulation of vertically stacked packages in a single step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked in a semiconductor package to increase mounting density, then the quantity of chips per package is improved, but void traps occur during the molding process leading to defects
Solution Approach 1:
The package substrate is segmented by forming through-holes that divide the molding cavity into separate regions. This segmentation allows the molding material to flow through the holes and eliminate voids that would otherwise form between stacked chips, resolving the contradiction between high chip density and molding quality.
Solution Approach 2:
Through-holes act as intermediary channels that facilitate the flow of molding material between stacked chips. These holes serve as mediators that enable complete encapsulation by allowing resin to penetrate and fill void spaces, thereby preventing defect formation while maintaining high chip mounting density.
2Reliability
If a mold film is used to cover and encapsulate stacked semiconductor chips, then complete encapsulation and product reliability are improved, but the molding process becomes more complex
Solution Approach 1:
Through-holes are formed in the package substrate before the molding process begins. This preliminary action prepares the structure to facilitate subsequent molding by pre-establishing channels for material flow, thereby simplifying the actual molding process while ensuring complete encapsulation and high reliability.
Solution Approach 2:
The package substrate is designed with porous characteristics through the formation of through-holes. This porous structure enables the molding material to flow through and completely encapsulate stacked chips, achieving high reliability without requiring excessively complex molding procedures, as the holes naturally guide the material flow.
3Reliability
If through-holes are formed in package substrates to discharge voids during molding, then void trap prevention is improved, but the manufacturing process complexity increases
Solution Approach 1:
The package substrate is segmented into multiple regions by forming through-holes, which divide the molding cavity. This segmentation creates natural pathways for void evacuation during molding, improving reliability while adding only a single fabrication step that integrates well with existing manufacturing processes.
Solution Approach 2:
The through-holes serve multiple functions: they act as structural support elements, provide electrical isolation, and facilitate void discharge during molding. This multi-functionality means that a single structural modification achieves multiple goals, improving reliability without proportionally increasing manufacturing complexity.
Data Source
AI summary
Semiconductor packages and methods of fabricating the same are provided. The semiconductor package includes a first package substrate including a first area, a first semiconductor chip mounted on the first area, a second package substrate disposed on an upper surface of the first semiconductor chip and including a second area and a first hole penetrating through the second area, a second semiconductor chip mounted on the second area, a connection member electrically connecting the first package substrate and the second package substrate and between the first package substrate and the second package substrate, and a mold film covering the second semiconductor chip on the second package substrate, filling the first hole, and covering the first semiconductor chip and the connection member on the first package substrate.