Stacked Semiconductor Package Venting for Void-Free Molding

Solution Overview

Problem

Semiconductor packages with multiple stacked chips face issues of void traps during molding, leading to defects and reduced reliability.

Innovation Solution

A semiconductor package design with penetrating holes in the package substrates and a mold film covering the chips and connection members, allowing voids to be discharged during encapsulation, enhancing reliability and enabling simultaneous encapsulation of multiple stacked chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple semiconductor chips are mounted in one semiconductor package to increase functionality, then the functionality and integration density are improved, but void traps occur during molding process leading to defects

Engineering Contradiction:

ImprovefunctionalityVSAvoiddefect-free molding

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

Penetrating holes are formed in the package substrate before mounting the semiconductor chips and performing molding. This preliminary action creates escape paths for voids before the molding process begins, preventing void trap defects while maintaining the ability to mount multiple chips for enhanced functionality

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The package substrate is segmented by forming multiple penetrating holes that divide the molding cavity into separate regions. This segmentation allows mold resin to flow more effectively and prevents large voids from forming during molding of multi-chip packages, thereby improving reliability without sacrificing the functionality gained from multiple chips

Inventive Principle:

Principle #1Segmentation

2Productivity

If many semiconductor chips are mounted in one semiconductor package to increase integration density, then the area utilization is improved, but void traps occur during molding process

Engineering Contradiction:

Improvearea utilizationVSAvoidvoid trap prevention

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

Penetrating holes are formed in the package substrate before mounting the semiconductor chips and performing molding. This preliminary action creates escape paths for voids before the molding process begins, preventing void trap defects while maintaining the ability to mount multiple chips for enhanced functionality

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The package substrate is designed with a porous structure featuring multiple penetrating holes that allow mold resin to flow through and carry voids away during the molding process. This porous design enables effective void evacuation while maintaining structural integrity and supporting high area utilization with multiple chips

Inventive Principle:

Principle #31Porous materials

3Reliability

If a mold film is formed to cover multiple stacked chips, then the encapsulation is improved, but voids become trapped inside the mold film

Engineering Contradiction:

Improveencapsulation qualityVSAvoidvoid traps

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

Penetrating holes are formed in the package substrate before mounting the semiconductor chips and performing molding. This preliminary action creates escape paths for voids before the molding process begins, preventing void trap defects while maintaining the ability to mount multiple chips for enhanced functionality

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The penetrating holes effectively extract and remove voids from the molding cavity during the molding process. By providing continuous escape paths through the substrate, voids are extracted from the encapsulation region and prevented from becoming trapped inside the mold film, thereby improving encapsulation quality without void traps

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentEP4379798B1Semiconductor package and method of fabricating the same

Publication Date: 2025.08.27 SAMSUNG ELECTRONICS CO LTD

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AI summary

Semiconductor packages and methods of fabricating the same are provided. The semiconductor package includes a first package substrate including a first area, a first semiconductor chip mounted on the first area, a second package substrate disposed on an upper surface of the first semiconductor chip and including a second area and a first hole penetrating through the second area, a second semiconductor chip mounted on the second area, a connection member electrically connecting the first package substrate and the second package substrate and between the first package substrate and the second package substrate, and a mold film covering the second semiconductor chip on the second package substrate, filling the first hole, and covering the first semiconductor chip and the connection member on the first package substrate.