Stacked Semiconductor Package Structure for Warpage Buffering
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Solution Overview
Problem
The increasing demand for smaller and lighter electronic components in portable devices necessitates a semiconductor package that can efficiently integrate multiple semiconductor chips while enhancing reliability and reducing size.
Innovation Solution
A semiconductor package design featuring vertically stacked semiconductor chips on a substrate with pillars, an adhesive layer, and protective layers, where the thickness of the protective layers is strategically optimized to provide structural support and stress buffering, along with a mold layer covering the chip stack and filling spaces between pillars, enhancing reliability and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated in a single package, then functionality and performance are improved, but package size increases
Solution Approach 1:
The patent transitions from horizontal arrangement of semiconductor chips to vertical stacking in the thickness direction, enabling multiple chips to be integrated within a compact footprint. This dimensional change allows the package to maintain small area while accommodating multiple functional chips, directly resolving the contradiction between enhanced functionality and increased package size.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are stacked vertically within the package body, with each chip positioned above the previous one in the thickness direction. This nesting approach allows multiple independent functional units to occupy overlapping spatial projections, achieving high integration density without increasing the package's planar dimensions.
2Productivity
If the number of semiconductor chips in a package increases, then performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the package into modular units consisting of individual semiconductor chips that can be independently manufactured and then vertically stacked. Each chip serves as a separate functional module, allowing parallel manufacturing processes and simplifying the overall production workflow despite the increased number of components, thereby improving performance without proportionally increasing manufacturing complexity.
3Reliability
If protective layers are added between chips and pillars, then reliability is improved, but package size increases
Solution Approach 1:
The patent employs thin protective film layers positioned between the semiconductor chips and the pillars. These thin films provide essential mechanical protection and stress distribution while occupying minimal space in the thickness direction, thereby enhancing structural reliability without significantly increasing the overall package volume.
Data Source
AI summary
A semiconductor package includes a chip stack comprising semiconductor chips vertically stacked on a substrate in a first direction perpendicular to a top surface of the substrate, pillars between the substrate and the chip stack, an adhesive layer on a bottom surface of a lowermost semiconductor chip of the semiconductor chips, a first lower protective layer between the adhesive layer and the pillars, a second lower protective layer between the first lower protective layer and the adhesive layer, and a mold layer covering the chip stack and filling a space between the pillars. A thickness of the second lower protective layer in the first direction is greater than a thickness of the adhesive layer in the first direction.