Stacked Semiconductor Package Structure for Wafer-Level Warpage
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Solution Overview
Problem
Semiconductor packages experience warpage issues, which affect reliability and yield, particularly during wafer-level manufacturing and testing.
Innovation Solution
A semiconductor package design that includes a second encapsulant covering the side surfaces of a metal post on the bottom surface of a first semiconductor chip, along with a redistribution substrate and encapsulant structures, to control warpage by adjusting the neutral axis of stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are vertically stacked to reduce device size and weight, then integration density and performance are improved, but warpage and reliability issues worsen
Solution Approach 1:
The patent changes the physical parameters of the package structure by introducing a through-substrate via (TSV) that extends through the entire substrate thickness, and by adding a specific encapsulant structure that wraps around the TSV. This modifies the stress distribution parameters and neutral axis position to compensate for warpage caused by vertical stacking, thereby improving reliability while maintaining the compact 3D structure.
Solution Approach 2:
The patent employs composite material structures including the combination of conductive materials (copper or tungsten) for the TSV, insulating materials for the encapsulant, and multiple semiconductor chips with different material properties. This composite approach allows optimization of each layer's properties to balance thermal expansion coefficients and mechanical stresses, reducing warpage in the vertically stacked configuration.
2Productivity
If wafer-level manufacturing is used to increase productivity, then manufacturing efficiency is improved, but warpage control and testing accuracy worsen
Solution Approach 1:
The patent segments the substrate into multiple functional regions with the TSV providing vertical interconnection through distinct layers. The encapsulant is segmented to specifically cover the TSV region while leaving other areas exposed or differently treated. This segmentation allows wafer-level processing to be applied uniformly across the substrate while the TSV-encapsulant structure locally addresses warpage control, enabling both high productivity and precision.
3Strength
If encapsulant material is added to fill spaces and protect chips, then structural support and protection are improved, but stress distribution and neutral axis position worsen
Solution Approach 1:
The encapsulant acts as an intermediary element that mediates between the TSV and the external environment, as well as between different substrate layers. It provides mechanical support and protection to the TSV while its specific placement and material properties are designed to create a balanced stress distribution that positions the neutral axis optimally, preventing both excessive stress concentration and insufficient support.
Data Source
AI summary
Provided is a semiconductor package with improvement in warpage thereof and a method of fabricating the semiconductor package. The semiconductor package includes a first semiconductor chip, a redistribution substrate on the first semiconductor chip, a second semiconductor chip on the redistribution substrate, a first encapsulant encapsulating the second semiconductor chip, on the redistribution substrate, a metal post arranged on a top surface of the first semiconductor chip, and a second encapsulant covering side surfaces of the metal post, on the bottom surface of the first semiconductor chip.