Stacked Semiconductor Package Backside Layout for Warpage Reduction
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Solution Overview
Problem
Existing semiconductor packages face challenges in increasing reliability and durability due to warpage caused by differences in thermal expansion between the front and back surfaces of stacked semiconductor chips.
Innovation Solution
Incorporating redistribution patterns on the back surfaces of semiconductor chips to reduce the thermal expansion mismatch, thereby minimizing or preventing warpage and enhancing chip reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are stacked sequentially to increase integration density, then productivity and miniaturization are improved, but warpage occurs due to thermal expansion mismatch between front and back surfaces
Solution Approach 1:
The patent applies local quality by adding redistribution patterns specifically on the back surface of the semiconductor chip where thermal stress concentrates. These patterns are not uniformly distributed across the entire chip but are strategically placed in regions experiencing thermal expansion mismatch, providing localized compensation for warpage while maintaining the stacked configuration for high integration density.
Solution Approach 2:
The patent changes physical parameters by introducing redistribution patterns with specific geometric characteristics (width of 10 μm to 100 μm, thickness of 5 μm or less, area ratio of 10% to 50% relative to bonding pads). These parameter adjustments create thermal compensation that counteracts warpage while preserving the stacked chip architecture for improved productivity.
2Reliability
If redistribution patterns are added on the back surface to reduce thermal expansion mismatch, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies partial action by implementing redistribution patterns only on the back surface of the chip rather than modifying the entire chip structure. The patterns cover a controlled area ratio of 10% to 50% relative to the bonding pads, providing sufficient thermal compensation to reduce warpage while avoiding excessive complexity that would arise from comprehensive structural modifications.
Solution Approach 2:
The patent manages complexity by carefully controlling the parameters of the redistribution patterns: width between 10 μm to 100 μm, thickness of 5 μm or less, and area ratio of 10% to 50%. These constrained parameter ranges ensure the patterns provide effective warpage reduction without creating excessive device complexity or manufacturing difficulty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The redistribution patterns on the back surfaces of semiconductor chips effectively reduce warpage, leading to increased reliability and yield of the semiconductor package.
Implementation Method 1
warpage caused by differences in thermal expansion between the front and back surfaces of stacked semiconductor chips
Data Source
AI summary
A semiconductor package includes a plurality of semiconductor chips stacked sequentially. Each semiconductor chip includes a substrate including a back surface and a front surface which are opposite to each other, a plurality of first back conductive pads disposed on the back surface, a plurality of second back conductive pads disposed on the back surface, and a redistribution pattern disposed on the back surface and disposed between the plurality of second back conductive pads.