Stacked Semiconductor Package Layout for Warpage Stress Relief
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Solution Overview
Problem
The challenge in the semiconductor industry is to create compact, lightweight, and high-performance semiconductor packages that can accommodate multiple chips stacked vertically while minimizing transmission loss and mechanical damage due to warpage in the base structure.
Innovation Solution
A semiconductor package design that includes a base structure with multiple semiconductor chips stacked vertically, where each chip has different widths based on the presence or absence of scribe regions, allowing for hybrid bonding and dielectric bonding to reduce transmission loss and distribute stress effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are stacked vertically to achieve higher performance and larger capacity, then the functionality and integration density are improved, but transmission loss increases and mechanical damage from warpage becomes more severe
Solution Approach 1:
The patent applies asymmetry by configuring semiconductor chips with different widths in the first direction (direction of motion) across the stack. Specifically, chips at different positions have different widths, with the width varying according to their location in the stack. This asymmetric width configuration reduces stress concentration and minimizes warpage-induced mechanical damage while maintaining effective electrical connection between chips, thereby resolving the contradiction between integration density and reliability.
2Weight of moving object
If semiconductor chips are stacked vertically to achieve miniaturization and light weight, then the package size and weight are reduced, but stress concentration from warpage increases
Solution Approach 1:
The patent employs asymmetry by designing chips with position-dependent widths in the first direction. Chips closer to the base structure have different widths compared to chips at higher positions in the stack. This asymmetric configuration distributes stress more evenly throughout the stack, preventing stress concentration at specific locations while maintaining the compact, lightweight vertical architecture.
3Ease of manufacture
If uniform width chips are used in the stack, then manufacturing is simplified, but stress distribution becomes uneven leading to warpage damage
Solution Approach 1:
The patent applies local quality by configuring each chip with a specific width in the first direction according to its position in the stack. Rather than using uniform widths, each chip's width is locally optimized based on its location - chips at different heights have different widths to achieve optimal stress distribution. This localized differentiation improves stress distribution and prevents warpage while remaining compatible with standard semiconductor manufacturing processes.
Data Source
AI summary
A semiconductor package includes a base structure and a plurality of semiconductor chips disposed on the base structure. Each of the plurality of semiconductor chips has a chip region. The plurality of semiconductor chips are stacked in a vertical direction such that chip regions at least partially overlap each other. In the stack of the plurality of semiconductor chips, each of the plurality of semiconductor chips has a first width in a first direction and a second width in a second direction. The plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip, having scribe regions on opposite sides of each of the chip regions. A first width of the first semiconductor chip is greater than a first width of the second semiconductor chip.