Stacked Semiconductor Package Layout for Warpage and Thermal Control
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving a compact size while maintaining effective electrical connections and thermal management, particularly due to warpage issues caused by differences in thermal expansion coefficients between the package substrate and semiconductor chips.
Innovation Solution
A semiconductor package design featuring a package substrate with a recessed portion for the lower semiconductor chip, where the upper semiconductor chip has a greater width and is connected using first and second bumps with different pitches and heights, along with an under-fill layer to encapsulate the bumps and enhance thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor chips are stacked to increase integration and operating speeds, then the functionality and performance of the semiconductor package are improved, but the package thickness increases
Solution Approach 1:
The patent applies nesting by placing the lower semiconductor chip inside a recessed portion of the package substrate, and then positioning the upper semiconductor chip on top of the lower chip. This nested arrangement allows both chips to occupy a compact vertical space, achieving high integration while minimizing the overall package thickness.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking semiconductor chips in a layered configuration. The recessed portion in the package substrate creates a stepped structure that accommodates the lower chip at a different vertical level than the upper chip, effectively using three-dimensional space to reduce the package footprint while maintaining stacking capability.
2Reliability
If different sized chips are stacked with bumps of different pitches, then the electrical connections between chips are improved, but the manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by using different bump pitches for different connection interfaces. Specifically, the first bumps connecting the upper chip to the package substrate have a first pitch, while the second bumps connecting the upper chip to the lower chip have a second pitch that is less than the first pitch. This localized adaptation of bump spacing optimizes electrical connections for each specific interface while managing the complexity through targeted design choices.
3Temperature
If the upper semiconductor chip has a greater width than the lower chip, then the thermal management and electrical connection area are improved, but the package size increases
Solution Approach 1:
The patent utilizes nesting by placing the narrower lower chip inside the recessed portion of the package substrate, allowing the wider upper chip to extend beyond the lower chip's boundaries. This arrangement maximizes the thermal management area provided by the upper chip while keeping the overall package compact through the nested configuration of the lower components.
Data Source
AI summary
A semiconductor package comprising a package substrate that has a recessed portion on a top surface thereof, a lower semiconductor chip in the recessed portion of the package substrate, an upper semiconductor chip on the lower semiconductor chip and the package substrate and having a width greater than that of the lower semiconductor chip, a plurality of first bumps directly between the package substrate and the upper semiconductor chip, and a plurality of second bumps directly between the lower semiconductor chip and the upper semiconductor chip. A pitch of the second bumps is less than that of the first bumps.