Stacked Semiconductor Package With Wider Conductive Paths for Heat and Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in achieving improved electrical and thermal properties, particularly in the integration and connectivity of semiconductor chips, which affect reliability and durability.
Innovation Solution
A semiconductor package design featuring a first redistribution substrate with a lower semiconductor chip and through vias, laterally spaced apart conductive structures, and an upper semiconductor chip connected via wider conductive structures, enhancing electrical and thermal performance through optimized conductive pathways and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board, then the package structure is simple, but the electrical and thermal properties are insufficient
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional vertical interconnection by stacking multiple semiconductor chips with conductive structures extending through via holes. This vertical dimension enables improved electrical and thermal properties while maintaining a compact footprint.
Solution Approach 2:
The patent employs composite conductive structures combining multiple materials (e.g., copper pillars, solder bumps, conductive adhesives) to achieve both electrical connectivity and thermal management. The redistribution substrate also uses composite layered structures with dielectric and conductive layers.
2Reliability
If the conductive structure width is increased to reduce resistance and improve current supply, then electrical properties improve, but the device area increases
Solution Approach 1:
Instead of increasing conductor width in the planar direction, the patent extends conductive pathways vertically through multiple chip layers and via holes. This allows reduced resistance and improved current supply capability while maintaining a compact lateral footprint.
Solution Approach 2:
The patent implements nested conductive structures where conductive pillars, via holes, and interconnect layers are arranged concentrically or in nested configurations. This enables efficient current pathways through vertical stacking rather than lateral expansion.
3Reliability
If multiple conductive structures are laterally spaced apart from the semiconductor chip, then thermal management and electrical isolation are improved, but the manufacturing complexity increases
Solution Approach 1:
The patent positions conductive structures in the vertical dimension rather than requiring complex lateral positioning. Conductive pillars and via holes are formed through the chip thickness, enabling thermal management and electrical isolation without complex lateral spacing arrangements.
Solution Approach 2:
The patent forms conductive structures (pillars, via holes, interconnect layers) before mounting the semiconductor chips. This preliminary formation of conductive pathways simplifies the overall manufacturing process by establishing thermal and electrical management structures in advance rather than requiring complex post-assembly positioning.
Data Source
AI summary
A semiconductor package includes a first redistribution substrate, a lower semiconductor chip on the first redistribution substrate and a through via therein, a first lower conductive structure and a second lower conductive structure that are on the first redistribution substrate and are laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and the second lower conductive structure and coupled to the through via and the second lower conductive structure, and an upper conductive structure on the first lower conductive structure. A width of the second lower conductive structure is greater than a width of the through via.