Stacked Semiconductor Package Layout to Prevent Wire Bond Collisions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing package structures face issues with low yield and reliability due to wire collisions and interference caused by consistent heights of electrical connection portions, leading to increased time delay and difficulty in the wire bonding process.
Innovation Solution
The package structure features electrical connection portions with increasing heights on the same side of the stack, with wires connected to these portions positioned farther away from the stack as the layer depth increases, reducing collisions and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical connection portions have consistent heights, then the structure is simple and easy to manufacture, but wire collisions and interference occur leading to low yield and reliability
Solution Approach 1:
The patent applies asymmetry by designing electrical connection portions with different heights corresponding to different semiconductor device layers. Specifically, the electrical connection portions are configured such that those connected to higher layers are positioned farther from the stack and have different heights, creating an asymmetric arrangement that prevents wire collisions while maintaining manufacturing feasibility through selective height adjustment of connection portions.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional spatial arrangement by varying the heights and lateral positions of electrical connection portions. This dimensional change allows wires to be routed at different vertical levels, eliminating collisions that would occur in a flat configuration while preserving structural simplicity through systematic height variation.
2Area of stationary object
If electrical connection portions are positioned closer to the stack, then the operating space is reduced, but wire collisions and interference increase
Solution Approach 1:
The patent applies local quality by positioning electrical connection portions at different lateral distances from the stack based on their specific function and the layer they connect to. Connection portions for higher layers are positioned farther away, while those for lower layers are closer, creating a localized optimization that reduces wire collisions without unnecessarily increasing the overall operating space.
3Reliability
If wires are routed with larger height differences, then wire collisions are reduced, but time delay increases
Solution Approach 1:
The patent applies parameter changes by systematically varying the height parameter of electrical connection portions to optimize the balance between wire collision prevention and signal transmission delay. The height differences are carefully controlled and adjusted based on the specific layer connections required, ensuring sufficient separation to prevent collisions while minimizing excessive height variations that would increase wire length and transmission delay.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances yield and reliability by minimizing wire collisions and interference, reduces the required operating space, and decreases time delay, while allowing for a more compact package structure.
Implementation Method 1
forming a plurality of wires by means of a wire bonding process, the plurality of wires being electrically connected to each of the plurality of electrical connection portions and a corresponding one of the plurality of semiconductor devices
Data Source
AI summary
Embodiments relate to the field of semiconductors, and provide a package structure and a method for fabricating the same. The package structure includes: a stack including a plurality of semiconductor devices stacked; a plurality of electrical connection portions positioned on a same side of the stack, each of the electrical connection portions being electrically connected to a corresponding semiconductor device, wherein in a direction distant from the stack, heights of different electrical connection portions gradually increase; and a plurality of wires electrically connected to each of the electrical connection portions and a corresponding semiconductor device, wherein the higher a layer where one semiconductor device is positioned in the stack, the farther one electrical connection portion connected to this semiconductor device is away from the stack. At least yield and reliability of the package structure can be improved while satisfying development of miniaturization of the package structure.