Multi-chip Stacked Package Wire Embedding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-chip stacked packages face issues with bonding wire collapse and deformation, leading to electrical shorts and trapped bubbles due to inadequate encapsulation and uneven curing of die-attaching materials, which complicates the manufacturing process and increases costs.
Innovation Solution
The use of patterned die-attaching bars that partially embed bonding wires, creating a central gap for uniform encapsulation and controlling the viscosity and curing level, preventing wire collapse and deformation while allowing for increased horizontal wire length without increasing package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bonding wires are extended horizontally to connect multiple chips, then more chips can be stacked with better uniform bonding wire lengths, but the risk of wire sweeping and electrical short increases
Solution Approach 1:
The patent introduces die-attaching material as an intermediary substance that fills the space around bonding wires during chip stacking. This material acts as a mediator that prevents wire sweeping by providing physical support and isolation, allowing extended horizontal wire connections without increasing electrical short risk.
Solution Approach 2:
The patent applies preliminary protective measures by pre-positioning die-attaching material before wire bonding operations. This preliminary anti-action prevents potential wire collapse and deformation before they can occur, enabling safer extension of bonding wires across multiple chips.
2Manufacturing precision
If die-attaching material is made softer and more fluid-like to prevent wire collapse, then wire deformation is reduced, but volatile materials become trapped causing bubbles and uneven curing
Solution Approach 1:
The patent performs preliminary wire bonding before applying and curing the die-attaching material. This sequence ensures wires are already in their final positions and configurations before the material is applied, preventing wire collapse while allowing the material to be applied in a controlled manner that avoids trapping volatile materials.
Solution Approach 2:
The patent controls the viscosity and curing parameters of the die-attaching material to optimize both wire support and volatile material release. By carefully managing these parameters during application and curing, the patent achieves wire deformation prevention without trapping bubbles, resolving the contradiction between material softness and curing uniformity.
3Productivity
If bonding wires are made longer to connect more chips, then stacking capacity increases, but wire collapse and deformation during chip attaching increases
Solution Approach 1:
The patent applies die-attaching material as a cushioning substance before final chip attachment. This material provides mechanical support and cushioning for extended bonding wires, preventing collapse and deformation during the chip stacking process while enabling increased stacking capacity through longer wire connections.
4Strength
If peripheries of die-attaching material are fully cured first, then adhesion is improved, but volatile materials at center become blocked causing incomplete curing
Solution Approach 1:
The patent performs wire bonding before applying die-attaching material, establishing a preliminary action sequence that prevents subsequent issues. By completing wire positioning first, the material application and curing process can proceed without interfering with wire integrity, allowing controlled curing that maintains both adhesion and uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively secures bonding wires, reduces trapped bubbles, and enhances package reliability by maintaining uniform viscosity and curing, avoiding electrical shorts and simplifying the manufacturing process while meeting cost and thickness requirements.
Implementation Method 1
a wafer-level die-attaching material (FOW film) is pre-formed on the second back surface (152) of the second chip (150) to attach the second chip (150) to the first chip (120 where the wafer-level die-attaching material (130) is partially cured paste, i.e., B-stage paste, to partially encapsulate the bonding wires (140)
Implementation Method 2
The first bonding pads (123) of the first chip (120) are electrically connected to the chip carrier (110) by a plurality of bonding wires (140)
Implementation Method 3
a wafer-level die-attaching material (FOW film) is pre-formed on the second back surface (152) of the second chip (150) to attach the second chip (150) to the first chip (120)
Data Source
AI summary
A multi-chip stacked package primarily comprises a chip carrier, a first chip disposed on the chip carrier, a plurality of die-attaching bars, a second chip stacked on the first chip by the adhesion of the die-attaching bars, and a plurality of bonding wires electrically connecting the first chip to the chip carrier. The die-attaching bars are formed on the first chip in a specific pattern and have an adhesive surface away from the first chip for adhering the second chip. The bonding wires have a loop height lower than the adhesive surface in a manner that specific sections of the bonding wires are embedded in the corresponding die-attaching bar from the adhesive surface. Accordingly, the die-attaching bars can modify and fasten the bonding wires in advance to avoid collapse and deformation of the bonding wires during stacking of the second chip and encapsulating processes.