Stacked Semiconductor Package Layout Without Wire Crossing
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Solution Overview
Problem
Traditional wBGA packages with single DRAM chips are unable to handle high data rates due to the need for swapping and crossing of bonding wires when stacking multiple chips, leading to a high risk of short circuits.
Innovation Solution
A semiconductor package design that includes multiple substrates and semiconductor chips with bonding wires positioned in windows, allowing direct electrical connections without pad swapping, using conductive foils and vias for efficient stacking and bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional wBGA method is used to stack multiple DRAM chips, then multiple chips can be packaged, but bonding wires must be swapped and crossed causing high risk of short circuits
Solution Approach 1:
The patent divides the package into multiple substrates (first substrate, second substrate) with windows that separate the bonding wire paths. This segmentation allows independent routing of bonding wires for different chips without crossing, eliminating the short circuit risk while maintaining multi-chip packaging capability.
Solution Approach 2:
The patent introduces a vertical stacking dimension with substrates positioned at different heights. The first substrate supports the first DRAM chip, while the second substrate supports the second DRAM chip. This three-dimensional arrangement allows bonding wires to connect vertically through windows without horizontal crossing, resolving the contradiction between multi-chip packaging and short circuit prevention.
2Quantity of substance
If bonding pad swapping is performed to stack chips, then multiple chips can be connected, but manufacturing complexity and cycle time increase
Solution Approach 1:
The patent pre-configures substrates with windows and bonding pads in specific positions before chip stacking. The first substrate has a first window and bonding pads arranged to receive bonding wires directly, and the second substrate has a second window and bonding pads positioned to align with the first. This preliminary arrangement eliminates the need for bonding pad swapping during manufacturing, reducing cycle time while enabling multi-chip stacking.
Solution Approach 2:
The patent introduces substrates with windows as intermediary structures between DRAM chips. These substrates provide bonding pads and window openings that facilitate direct bonding wire connections from each chip to its corresponding substrate without requiring pad swapping. This intermediary structure simplifies the manufacturing process and reduces cycle time.
3Reliability
If bonding wires are crossed to connect chips in traditional wBGA, then electrical connections can be established, but the possibility of short circuit increases
Solution Approach 1:
The patent segments the bonding wire paths by providing separate windows in the substrates. The first bonding wire passes through the first window to connect the first DRAM chip to the first substrate, while the second bonding wire passes through the second window to connect the second DRAM chip to the second substrate. This physical segmentation prevents wire crossing and eliminates short circuit risk while maintaining reliable electrical connections.
Solution Approach 2:
The substrates with windows act as intermediaries that guide and separate bonding wires. The windows provide dedicated pathways for each bonding wire, preventing them from crossing or coming into contact. This intermediary structure ensures reliable electrical connections while eliminating the harmful effect of potential short circuits.
Data Source
AI summary
A semiconductor package includes a first substrate, a first semiconductor chip, a first bonding wire, a second substrate, a second semiconductor chip and a second bonding wire. The first substrate has a window through a center portion of the first substrate. The first semiconductor chip is located on the first substrate. The first bonding wire is in the window of the first substrate and electrically connects to the first semiconductor chip and the first substrate. The second substrate is located on the first semiconductor chip, and has a window through a center portion of the second substrate. The second substrate electrically connects to the first substrate. The second semiconductor chip is located on the second substrate. The second bonding wire is in the window of the second substrate and electrically connects to the second semiconductor chip and the second substrate.