Stacked Semiconductor Package Layout With Reduced Bonding Wire Space
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Solution Overview
Problem
There is a demand for high-performance and high-capacity semiconductor packages with reduced size to accommodate a greater number of chips, while maintaining a lightweight and thin profile.
Innovation Solution
A semiconductor package design featuring a package substrate with an insulating layer and interconnection circuit, stacked semiconductor chips connected by a support structure and connection structures, including a first connection structure extending in one direction and a second connection structure intersecting this direction, with a conductive layer and barrier layer, to reduce the vertical space occupied by bonding wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to connect upper pads to connection pads of semiconductor chips, then electrical connection is achieved, but the package size increases due to the space occupied by bonding wires
Solution Approach 1:
The patent extracts and eliminates the bonding wire component from the package structure. Instead of using traditional bonding wires to connect upper pads to connection pads, the invention uses direct conductive paths through the support structure and connection structures, removing the need for separate bonding wire elements and thereby reducing package volume.
Solution Approach 2:
The patent transitions from a planar connection approach (bonding wires extending horizontally) to a vertical/dimensional connection approach where connection structures extend through the support structure in the vertical direction, allowing electrical connections to be made through the thickness of the package rather than around it, thus reducing the horizontal footprint.
2Quantity of substance
If multiple semiconductor chips are stacked to increase capacity, then chip integration is improved, but the vertical height of the package increases
Solution Approach 1:
The patent implements a nested structure where semiconductor chips are stacked vertically within a compact footprint. The support structure and connection structures are nested between the chips, with connection structures extending through the support structure to establish electrical connections between adjacent chips. This nesting allows multiple chips to be integrated in a vertical stack without proportionally increasing package height, as the connection elements are integrated within the inter-chip spaces.
3Volume of stationary object
If connection structures extend through the support structure to reduce bonding wire space, then package size is reduced, but manufacturing complexity increases
Solution Approach 1:
The support structure serves multiple functions: it provides mechanical support for the semiconductor chips, establishes electrical connections between chips through integrated connection structures, and eliminates the need for separate bonding wire elements. The connection structures simultaneously provide both structural support and electrical connectivity, reducing the total number of components and simplifying the overall manufacturing process despite the integrated design.
Data Source
AI summary
A semiconductor package includes a package substrate including an insulating layer, an interconnection circuit, and upper pads and lower pads electrically connected through the interconnection circuit, a plurality of semiconductor chips stacked including connection pads, a support structure contacting a side surface of a first semiconductor chip, which is an uppermost one among the plurality of semiconductor chips and at least a portion of an upper surface of a second semiconductor chip, which is one among the plurality of semiconductor chips below the first semiconductor chip, a first connection structure connecting the upper pads of the package substrate to the connection pads of the second semiconductor chip, a second connection structure connecting the connection pads of the first semiconductor chip to the connection pads of the second semiconductor chip, and an encapsulant covering the plurality of semiconductor chips, the first connection structure, and the second connection structure.