Stacked Semiconductor Package Layout to Prevent Wire Sweeping
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving miniaturization, high performance, high capacity, and high reliability while minimizing damage during the manufacturing process, particularly due to issues with interconnectors such as overhang and wire sweeping.
Innovation Solution
A semiconductor package design featuring a multi-layer molding structure and the use of bumps and wires as interconnectors, with specific alignment and arrangement to minimize overhang and maintain wire length, ensuring a high-quality molding process and preventing die cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked in multiple stages to achieve miniaturization and high capacity, then the package size is reduced and capacity is increased, but the complexity of the manufacturing process increases and the risk of damage during manufacturing increases
Solution Approach 1:
The manufacturing process is divided into multiple stages: forming a first sub-package with first semiconductor chips, forming a second sub-package with second semiconductor chips on a carrier substrate, and then combining them. This segmentation allows complex multi-chip stacking to be broken down into manageable steps, reducing manufacturing complexity while achieving high capacity.
Solution Approach 2:
Sub-packages are pre-formed on carrier substrates before final assembly. The carrier substrate provides temporary support during manufacturing, and separation grooves are pre-formed to facilitate clean separation. This preliminary action prevents damage during the stacking process while enabling high-density chip arrangements.
2Reliability
If vertical interconnectors are used to connect stacked semiconductor chips, then high performance and high capacity are achieved, but the possibility of damage during manufacturing increases due to overhang and wire sweeping issues
Solution Approach 1:
A molding layer is introduced as an intermediary substance between the semiconductor chips and carrier substrate. This molding layer fills the separation groove and provides mechanical support to the vertical interconnectors (wires and bumps), preventing wire sweeping and overhang damage during the manufacturing process while maintaining electrical connectivity.
Solution Approach 2:
The separation groove is pre-formed in the carrier substrate before wire bonding. This preliminary structural preparation prevents wire overhang by providing a defined path and support structure, eliminating the harmful effect of wire sweeping before it can occur during subsequent manufacturing steps.
Data Source
AI summary
A semiconductor package includes a package substrate, and a first plurality of semiconductor chips that is disposed on the package substrate and that includes at least two semiconductor chips. A semiconductor chip of the first plurality of semiconductor chips disposed closest to the package substrate may be connected to the package substrate by a bump, and a semiconductor chip of the first plurality of semiconductor chips disposed farthest from the package substrate may be connected to the package substrate by a wire.