Stacked Semiconductor Package Layout Without Wire Bonding
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Solution Overview
Problem
Existing semiconductor packages with stacked semiconductor chips face issues of thickness and complexity due to wire bonding, which complicates manufacturing and affects signal quality.
Innovation Solution
The semiconductor package employs reduced upper connection pads on a package substrate and uses patterned wires instead of wire bonding to connect stacked semiconductor chips, simplifying the manufacturing process and maintaining a thin profile while improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect stacked semiconductor chips, then electrical input/output can be established between chips and package substrate, but the semiconductor package becomes thicker and the manufacturing process becomes more complex
Solution Approach 1:
The patent extracts and eliminates the wire bonding process from the stacked semiconductor chip connection method. Instead of using separate wire bonding steps for each chip layer, the invention integrates all electrical connections into a single planar routing layer that distributes signals across the package substrate, thereby removing the complexity of multi-layer wire bonding while maintaining reliable electrical connections.
Solution Approach 2:
The patent transitions from three-dimensional wire bonding (vertical connections between stacked chips) to two-dimensional planar routing (horizontal connections across the substrate). This dimensional change allows multiple chip connections to be established simultaneously in a single layer, reducing both manufacturing complexity and package thickness while maintaining electrical connectivity.
2Reliability
If wire bonding is used for stacked semiconductor chips, then electrical connections can be established, but the package size increases and wiring defects increase
Solution Approach 1:
The patent replaces vertical wire bonding paths with horizontal planar routing paths on the package substrate. This dimensional transformation allows electrical connections to be made in a single plane rather than requiring vertical penetration through multiple chip layers, thereby reducing package thickness while maintaining connection reliability.
Solution Approach 2:
The patent merges multiple separate wire bonding operations into a single integrated planar routing structure. By combining all electrical connections between stacked chips and the package substrate into one continuous routing layer, the invention reduces the overall package thickness and minimizes the number of discrete connection points that could potentially fail.
3Reliability
If multiple upper connection pads are provided on package substrate for stacked chips, then all chips can be connected, but the package substrate area increases
Solution Approach 1:
The patent makes the single routing layer universal by designing it to serve multiple connection functions simultaneously. The planar routing structure is configured to distribute signals to multiple stacked chips through a shared infrastructure, allowing one routing layer to replace what would traditionally require multiple separate connection pads and wiring layers, thereby reducing the required substrate area.
Solution Approach 2:
The patent segments the routing function into a modular planar structure that can serve multiple chips independently while sharing common infrastructure. The routing layer is divided into distinct signal paths that can be independently configured for different chip connections, allowing efficient use of substrate area while maintaining reliable connections to all stacked chips.
Data Source
AI summary
Provided is a semiconductor package including a package substrate having a first upper connection pad and a second upper connection pad provided on a top surface of the package substrate, a semiconductor chip disposed on the package substrate, a second semiconductor chip provided on the first semiconductor chip, a plurality of first chip pads and a plurality of second chip pads provided on top surfaces of the first semiconductor chip and the second semiconductor chip, respectively, a plurality of first conductive patterns, a plurality of second conductive patterns, and a cross conductive pattern of which both ends are connected to the first conductive pattern, wherein the cross conductive pattern is provided on a top surface of the first semiconductor chip and the second conductive pattern, and the cross conductive pattern crosses the second cross conductive pattern.