Stacked Semiconductor Package Wiring for Signal Interference Isolation
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Solution Overview
Problem
Existing semiconductor packages face challenges in efficiently connecting and stacking chips while maintaining signal integrity and reducing electrical interference, particularly as the complexity and density of chip stacks increase.
Innovation Solution
The semiconductor package design includes a package substrate with alternately arranged bonding pads, multiple chip stacks with signal and power/ground pads arranged alternately, and specific wire connections that link the chip pads to the substrate and between chip stacks, thereby isolating signal and power/ground connections to reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chips are stacked densely to increase integration, then productivity and device functionality improve, but electrical interference between signal and power/ground connections increases
Solution Approach 1:
The bonding pads on the package substrate are segmented into distinct first bonding pads for signal connections and second bonding pads for power/ground connections, arranged in separate regions. This spatial segmentation prevents electrical interference while maintaining high chip stacking density by allowing independent routing of signal and power/ground paths.
Solution Approach 2:
The harmful electrical interference is extracted and eliminated by separating the signal and power/ground connection paths. The first wires connecting signal pads to first bonding pads are spatially separated from second wires connecting power/ground pads to second bonding pads, removing the source of interference while preserving integration density.
2Ease of manufacture
If signal and power/ground pads are arranged alternately on chips, then manufacturing simplicity is maintained, but electrical interference increases
Solution Approach 1:
While signal and power/ground pads are arranged alternately on individual chips for manufacturing simplicity, the patent segments their connections at the package level by directing signal pads through first wires to first bonding pads and power/ground pads through second wires to second bonding pads in separate regions, eliminating interference while maintaining pad arrangement simplicity.
Solution Approach 2:
The alternating pad arrangement on chips is resolved by transitioning to a two-dimensional separation in the wiring layer, where first wires and second wires are routed through different spatial paths and connection regions on the package substrate, maintaining manufacturing simplicity while eliminating electrical interference.
3Adaptability or versatility
If multiple wire connections are used to connect chip stacks to substrate, then connectivity and functionality improve, but device complexity increases
Solution Approach 1:
The wire connection structure is segmented into functionally distinct first wires for signal connections and second wires for power/ground connections, each with dedicated bonding pads and routing paths. This segmentation improves connectivity adaptability while managing complexity through systematic organization of connection types.
Solution Approach 2:
Multiple wire connections are managed by organizing them in different spatial dimensions on the package substrate, with first bonding pads and first wires occupying one region and second bonding pads and second wires occupying another region, improving connectivity while controlling complexity through spatial management.
Data Source
AI summary
A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.