Stacked Microelectronic Packages Using TPVs Instead of TSVs
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Solution Overview
Problem
The existing methods for fabricating microelectronic device assemblies with stacked semiconductor dice are costly and time-consuming due to the use of through substrate vias (TSVs), which require high-temperature thermocompression bonding and consume valuable space, especially as dice stacks increase in size and complexity.
Innovation Solution
The approach involves fabricating microelectronic device packages without TSVs, using through poly vias (TPVs) and fan-out package (FOP)-configured redistribution layers (RDLs) to connect conductive traces between stacked semiconductor dice, allowing for vertical interconnects through polymeric films and conductive materials, reducing the need for high-temperature bonding and minimizing space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermocompression bonding is used to connect stacked semiconductor dice, then reliable electrical and mechanical connections are achieved, but fabrication cost and time increase significantly
Solution Approach 1:
Conductive elements (pillars and pads) are pre-formed on the semiconductor dice before stacking. The conductive material is deposited and patterned in advance, so that when dice are stacked, the connections are already prepared and only require simple alignment and bonding, eliminating the need for complex high-temperature thermocompression bonding during assembly
Solution Approach 2:
The bonding process parameters are changed from high-temperature thermocompression bonding to lower-temperature alternative bonding methods. The conductive elements are designed to enable bonding at reduced temperatures and pressures, significantly reducing fabrication cost and time while maintaining connection reliability
2Reliability
If through substrate vias (TSVs) are used for vertical interconnection, then electrical connectivity between stacked dice is achieved, but valuable space is consumed and fabrication complexity increases
Solution Approach 1:
The conductive elements are extended beyond the edges of the semiconductor dice in the lateral dimension. This allows electrical connectivity to be achieved through alternative paths that do not require penetrating the substrate thickness, effectively utilizing the lateral space outside the die edges for vertical interconnection functionality
Solution Approach 2:
The TSV structure is extracted and replaced with external conductive paths. The conductive elements are positioned outside the substrate footprint, eliminating the need for space-consuming through-substrate vias while maintaining electrical connectivity between stacked dice
3Strength
If high-temperature thermocompression bonding is applied, then strong bonds are formed between conductive elements, but thermal budget is exceeded and alignment precision becomes difficult to maintain
Solution Approach 1:
The bonding temperature and pressure parameters are significantly reduced from conventional thermocompression bonding conditions. The conductive elements and substrate are designed to enable effective bonding at lower temperatures, preventing thermal damage and maintaining alignment precision throughout the bonding process
Data Source
AI summary
Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.