Stacked Semiconductor Pad Bonding With Debris-Trapping Cavities

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Solution Overview

Problem

Current semiconductor packaging technologies face challenges in achieving high-density, thin, and miniaturized semiconductor devices with improved electrical characteristics and driving stability, particularly in the integration of multiple semiconductor chips with reduced defects and enhanced reliability.

Innovation Solution

A semiconductor device design featuring a lower and upper structure with insulating layers and recesses, where the pads are bonded to form an integral monolithic layer, and metallic particles are collected into air gaps between the insulating layers to prevent debris-induced short circuits, allowing for improved electrical connectivity and stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple semiconductor chips are vertically stacked to achieve high-density integration, then the device capacity and integration density are improved, but the risk of debris-induced short circuits and manufacturing defects increases

Engineering Contradiction:

Improveintegration densityVSAvoidshort circuit risk

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent extracts and removes metallic debris particles from the bonding interface between insulating layers before final assembly, preventing potential short circuits while maintaining high-density vertical stacking of semiconductor chips

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary cleaning of metallic debris from the bonding interface before final chip stacking, preventing future short circuit issues while enabling high-density integration

Inventive Principle:

Principle #10Preliminary action

2Reliability

If bonding interface is cleaned to remove metallic debris, then electrical reliability is improved, but additional manufacturing steps and process complexity are introduced

Engineering Contradiction:

Improveelectrical reliabilityVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs a self-aligning cleaning mechanism where the cleaning structure automatically positions itself at the bonding interface during assembly, eliminating the need for complex external alignment systems and reducing overall manufacturing complexity

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The cleaning structure is designed to perform multiple functions: removing metallic debris, facilitating proper bonding alignment, and ensuring electrical insulation, thereby reducing the need for separate manufacturing steps

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230378110A1Semiconductor device and method of fabricating the same

Publication Date: 2023.11.23 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a semiconductor device including lower and upper structures. The lower structure includes a first substrate, a first pad on the first substrate, and a first insulating layer surrounding the first pad. The upper structure includes a second substrate, a second pad on the second substrate, and a second insulating layer surrounding the second pad. The upper and lower structures contact each other. The first and second pads contact each other. The first and second insulating layers contact each other. The first insulating layer includes a first recess adjacent the first pad, the second insulating layer includes a second recess that is adjacent the second pad and overlaps the first recess, and a cavity is defined by the first recess and the second recess, and particles of a metallic material constituting the first and second pads are in the cavity.