Stacked Semiconductor Pad Bonding With Grain-Size Interface Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high structural stability, electrical properties, and reduced failure rates, particularly in vertically stacked chip configurations.
Innovation Solution
A semiconductor device design featuring a lower and upper structure with pads bonded through an interfacial layer, where the pads and interfacial layer share a metallic material, and the interfacial layer has a different grain size, ensuring direct contact and minimal impurities for enhanced stability and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically stacked chip configuration is used to achieve high density integration, then integration density is improved, but structural stability deteriorates
Solution Approach 1:
The bonding interface is segmented into multiple functional layers including interfacial layer, first dielectric layer, and second dielectric layer. Each layer performs specific functions: interfacial layer for direct metal-to-metal bonding, dielectric layers for mechanical support and stress distribution. This segmentation allows the system to achieve both high integration density through effective bonding while maintaining structural stability through properly designed supporting layers.
Solution Approach 2:
The bonding structure uses composite material design with different grain sizes in the interfacial layer and pads. The interfacial layer has finer grain size for strong bonding, while pads have coarser grain size for mechanical strength. This composite approach at microstructural level enables simultaneous achievement of bonding strength and structural stability in vertically stacked configuration.
2Ease of manufacture
If pads with same grain size are used to simplify manufacturing, then manufacturing complexity is reduced, but bonding strength deteriorates
Solution Approach 1:
Different grain sizes are applied locally to different components: the interfacial layer has finer grain size for strong bonding, while the pads have coarser grain size for mechanical strength and easier manufacturing. This local quality differentiation allows each region to be optimized for its specific function while maintaining overall manufacturing feasibility through standardized processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances structural stability and electrical properties while reducing failure rates by providing strong bonding and minimal resistance, thus improving the reliability of vertically stacked semiconductor devices.
Implementation Method 1
The first pad and the second pad are bonded to each other across an interfacial layer to couple the upper structure and the lower structure to each other
Implementation Method 2
A plating process is performed. The plating process forms a conductive layer that fills the hole and covers the dielectric layer
Implementation Method 3
An argon (Ar) plasma treatment process is performed on the surface layer and the dielectric layer
Implementation Method 4
After the nitrogen plasma treatment process is performed, copper nitride (Cu4N) is formed on a top surface of the surface layer and silicon hydroxide (Si—OH) is formed on a top surface of the dielectric layer
Implementation Method 5
An annealing process is performed on the upper structure and the lower structure
Data Source
AI summary
A semiconductor device includes a lower structure and an upper structure on the lower structure. The lower structure includes a first semiconductor substrate, a first pad and a first dielectric layer. The first dielectric layer surrounds the first pad and exposes a top surface of the first pad. The upper structure includes a second semiconductor substrate, a second pad and a second dielectric layer. The second dielectric layer surrounds the second pad and exposes a bottom surface of the second pad. The first pad and the second pad are bonded to each other across an interfacial layer to couple the upper and lower structures to each other. The first and second pads and the interfacial layer include a same metallic material. The first and second pads have a substantially same average grain size and the interfacial layer has a different average grain size than the first and second pads.