Stacked Semiconductor Package Pad Structure for Heat Release

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Solution Overview

Problem

Semiconductor packages incorporating multiple chips face challenges in effectively releasing heat, leading to performance degradation due to inadequate heat dissipation.

Innovation Solution

The semiconductor package design includes a lower structure with a heat sink structure at the same height level as the pad structure, connected via a connection pattern that extends to expose the pad structure, allowing for improved heat dissipation by creating openings in the mold layer to enhance contact with the heat sink.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple chips are incorporated in a single package, then the capacity and functionality of the electronic product are improved, but heat generated inside the package becomes difficult to release, causing performance degradation

Engineering Contradiction:

Improvenumber of chipsVSAvoidheat dissipation

Core Design Contradiction:

Quantity of substanceVSTemperature

Solution Approach 1:

The patent introduces a vertical stacking arrangement where chips are arranged in multiple layers (lower structure and upper structure) connected through connection patterns. This three-dimensional configuration allows heat to be dissipated through multiple vertical pathways via heat sink structures in each layer, transforming the traditional planar heat dissipation into a multi-dimensional thermal management system that effectively handles heat from multiple chips.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If chips are stacked in multiple layers, then the package density is improved, but heat release becomes more difficult due to increased thermal accumulation

Engineering Contradiction:

Improvepackage densityVSAvoidheat release

Core Design Contradiction:

Volume of moving objectVSLoss of energy

Solution Approach 1:

The patent divides the multi-chip package into distinct structural segments - lower structure with lower chips, connection patterns, and upper structure with upper chips. Each segment contains its own heat sink structures that can independently dissipate heat. This segmentation allows heat from different chip layers to be managed separately through dedicated thermal pathways, preventing thermal accumulation even as package density increases.

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If connection patterns are used to electrically connect lower and upper structures, then the functionality and capacity of the package are improved, but the complexity of the package structure increases

Engineering Contradiction:

Improvepackage functionalityVSAvoidpackage structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The connection patterns in the patent serve multiple functions simultaneously: they provide electrical connectivity between lower and upper chip structures, act as mechanical support structures, and function as thermal management pathways through integrated heat sink structures. This multi-functionality reduces the need for separate dedicated components for each function, thereby managing structural complexity while enhancing package versatility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively enhances heat sink characteristics, preventing performance deterioration by efficiently releasing heat generated within the package, thereby improving the overall performance and reliability of semiconductor packages.

Implementation Method 1

a heat sink structure... efficiently releasing heat generated within the package

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

openings in the mold layer to enhance contact with the heat sink... efficiently releasing heat

Methodology Applied

Scientific EffectConvection: Convection

Data Source

PatentUS12057366B2Semiconductor devices including a lower semiconductor package, an upper semiconductor package on the lower semiconductor package, and a connection pattern between the lower semiconductor package and the upper semiconductor package

Publication Date: 2024.08.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.