Package-on-Package Stacked Subsystems with Integrated Passive Components
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Solution Overview
Problem
Current technologies face challenges in minimizing the size and weight of electronic products by reducing the board area consumed by semiconductor devices and passive components, with slow progress in shrinking package sizes.
Innovation Solution
The approach involves selecting passive electronic components from the board, assembling them onto a special substrate, and stacking this subsystem onto the active semiconductor device, utilizing flip-chip assembly and metal reflow bodies to connect the components, thereby adding components to the third dimension and minimizing electrical resistances and inductances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If passive components are assembled on a board in traditional layout, then board area is consumed for each component, but transitioning to package-on-package stacking reduces board area significantly
Solution Approach 1:
The patent transitions from two-dimensional board mounting to three-dimensional stacking by placing passive components on a separate substrate and stacking it onto the active device package. This vertical integration moves components from the board plane into the third dimension, dramatically reducing the board footprint while maintaining all necessary electrical connections through reflow bodies.
2Reliability
If wire bonding is used for interconnection, then assembly is simpler, but electrical resistance and inductance are higher; flip-chip assembly reduces resistance and inductance but increases assembly complexity
Solution Approach 1:
The patent extracts the interconnection method from traditional wire bonding and replaces it with flip-chip assembly using reflow bodies. This extraction eliminates the need for wire bonds and enables direct electrical contact between substrates, significantly reducing electrical resistance and inductance while improving signal integrity and power delivery.
3Area of stationary object
If components are placed in single layer on board, then manufacturing is simpler, but board area consumption is high; multi-layer stacking reduces board area but increases manufacturing complexity
Solution Approach 1:
The patent segments the electronic system into distinct functional modules: an active device package substrate and a passive component substrate. Each substrate is independently prepared and populated with its respective components, then joined together through stacking. This segmentation enables parallel manufacturing processes and simplifies the overall production while achieving three-dimensional integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method achieves significant reduction in board area and overall system thickness, offering improved speed, power capabilities, reduced manufacturing time, and enhanced product reliability by leveraging the third dimension for component stacking.
Implementation Method 1
Metal reflow bodies, such as solder balls, connect the active device stacked with the passive subsystem
Data Source
AI summary
A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more semiconductor chips stacked on top of each other, assembled on the substrate. The system further has a packaged passive subsystem (320) including a substrate with electrical contacts and passive electrical components, such as resistors, capacitors, and indictors. The passive subsystem is stacked with the active subsystems and connected to them by solder bodies.