Stacked Peaker Quadrature Load Modulation PA for Wide PBO Efficiency
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Solution Overview
Problem
Conventional quadrature combined load modulation power amplifiers face limitations in achieving high power-added efficiency and extended power backed off efficiency range due to constraints in breakdown voltage and increased peaker device periphery, which results in lower bandwidth and higher impedance transformation matching networks.
Innovation Solution
The use of stacked transistors in peaker amplifiers for quadrature combined load modulation power amplifiers allows for higher supply and peak power operation, increasing the power-added efficiency and power backed off efficiency range while maintaining bandwidth, by providing higher off-state peaker output impedance and reducing loading effects on the carrier amplifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If asymmetric Doherty amplifiers use larger peaker device periphery to extend PBO efficiency range, then power backed off efficiency range is improved, but bandwidth deteriorates due to higher impedance transformation matching networks
Solution Approach 1:
The patent transitions from increasing device periphery (2D scaling) to stacking devices in series (3D configuration). This vertical stacking approach increases the peak amplifier supply voltage capability without requiring larger device footprints, thereby avoiding the bandwidth degradation associated with large impedance transformation networks while still extending the PBO efficiency range.
Solution Approach 2:
The patent changes the supply voltage parameter by stacking devices to achieve higher voltage operation. This allows the peak amplifier to operate at higher voltages during peak power conditions, extending the efficient operating range into deeper power back-off regions without requiring larger device geometries that would compromise bandwidth.
2Power
If asymmetric supply operation increases peaker current to extend PBO efficiency range, then power backed off efficiency is improved, but device breakdown voltage constraint is violated
Solution Approach 1:
Instead of increasing current (horizontal approach), the patent stacks devices vertically to increase voltage capability. This allows the peak amplifier to achieve higher power output and extended PBO efficiency range through voltage multiplication rather than current increase, respecting the breakdown voltage constraints of individual devices.
Solution Approach 2:
The patent segments the voltage stress across multiple stacked devices rather than concentrating it in a single device. Each device in the stack operates within its breakdown voltage rating, while the series combination achieves the higher voltage operation needed for extended PBO efficiency range.
3Power
If conventional asymmetric design increases peaker transistor device size for greater than 6 dB PBO efficiency enhancement, then power backed off efficiency range is improved, but bandwidth is compromised
Solution Approach 1:
The patent achieves greater than 6 dB PBO efficiency enhancement through voltage stacking (vertical dimension) rather than device size scaling (horizontal dimension). This approach extends the efficiency range while maintaining the original device footprint and associated bandwidth characteristics.
Data Source
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AI summary
A load modulation amplifier (10) is disclosed having a first power amplifier (16) configured to amplify a first portion of a radio frequency signal below a threshold level. A second power amplifier (18) has an N stack of transistor devices configured in a cascode configuration to amplify a second portion of the radio frequency signal that is above the threshold level, wherein N is a counting number that is greater than one.