Stacked Photonics Die Layout With Bottom Optical Interconnect

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Solution Overview

Problem

Legacy photonics packaging systems face challenges with complex alignment, thermal solutions, and increased package size due to optical connections being positioned at the top, which complicates assembly and testing, and requires complex interconnect bridges and pigtails.

Innovation Solution

Incorporating an optical interconnect at the bottom of the photonics die, allowing for direct optical connections and reducing the need for vertical optical routing, which simplifies thermal management and package assembly by enabling a more compact and robust design with reduced interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If optical connections are positioned at the top of the package, then optical coupling is achieved, but device complexity and package size increase due to required interconnect bridges and pigtails

Engineering Contradiction:
Improveoptical couplingVSAvoidpackaging system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent inverts the conventional topology by positioning the optical interface at the bottom of the package instead of the top. This inversion eliminates the need for complex interconnect bridges and pigtails that dangle down from the top, thereby reducing packaging system complexity while maintaining optical coupling functionality.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent extracts and removes the unnecessary interconnect bridges and pigtails from the packaging system by repositioning the optical interface to the bottom, where direct optical connections can be made without requiring these additional components.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If optical connections are positioned at the top of the package, then optical coupling is achieved, but manufacturing complexity and testing difficulty increase

Engineering Contradiction:
Improveoptical couplingVSAvoidassembly and testing ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

By inverting the optical interface position to the bottom, the patent enables more straightforward assembly processes and testing procedures, eliminating the complexity associated with top-mounted optical connections that require precise alignment of interconnect bridges and pigtails.

Inventive Principle:
Principle #13The other way round (Inversion)

3Temperature

If thermal cooling features are pressed against the top of the package, then thermal management is achieved, but space for optical connectors is reduced

Engineering Contradiction:
Improvethermal managementVSAvoidavailable space for connectors
Core Design Contradiction:
TemperatureVSArea of stationary object

Solution Approach 1:

The patent resolves the space conflict by inverting the optical interface location to the bottom of the package, allowing thermal cooling features to occupy the top surface without encroaching on optical connector space. This separation of functions eliminates the need to choose between thermal management and optical connectivity space.

Inventive Principle:
Principle #13The other way round (Inversion)

4Adaptability or versatility

If integrated plugs are used to route optical signals, then space routing issues are resolved, but package size and complexity increase

Engineering Contradiction:
Improvespace routingVSAvoidpackage size
Core Design Contradiction:
Adaptability or versatilityVSVolume of stationary object

Solution Approach 1:

The patent extracts and eliminates the need for integrated plugs by positioning the optical interface at the bottom, where direct optical connections can be made without requiring additional routing components that would increase package size.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250020874A1Stackable photonics die with direct optical interconnect
Publication Date: 2025.01.16 INTEL CORP
  • US20250020874A1 patent drawing
  • US20250020874A1 patent drawing
  • US20250020874A1 patent drawing

AI summary

Embodiments described herein may be related to apparatuses, processes, and techniques related to incorporating photonics integrated circuitry into a base die, the base die including an optical interconnect at a bottom of the base die to transmit and to receive light signals from outside the base die. The top of the base die includes one or more electrical connectors that are electrically coupled with the photonics integrated circuitry. The base die may be referred to as the photonics die. A system-on-a-chip (SOC) may be electrically coupled with and stacked onto the top of the photonics die. Other embodiments may be described and/or claimed.