Stacked Photonics Chips Evanescent Light Coupling

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Solution Overview

Problem

The limited space on photonics chips for integrating optical and electronic components hinders the reduction of layout area, cost, and operational overhead, necessitating improved structures and fabrication methods for stacked photonics chips.

Innovation Solution

A structure comprising stacked photonics chips with a first waveguide core, a ring resonator, and a dielectric layer, where the second chip's waveguide core is positioned adjacent to the ring resonator, enabling efficient light transfer between chips without the need for grating couplers, which are sensitive to misalignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If components are integrated on a single photonics chip, then layout area and operational overhead are reduced, but the available space for placing optical and electronic components becomes limited

Engineering Contradiction:
Improveintegration complexityVSAvoidavailable space for components
Core Design Contradiction:
Device complexityVSArea of stationary object

Solution Approach 1:

The patent transitions from planar integration to three-dimensional stacked architecture by bonding multiple photonics chips together. This vertical stacking approach provides additional spatial dimension for component placement, effectively increasing the available space without increasing the footprint area of individual chips.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The system divides the photonic functionality across multiple separate chips that are stacked and bonded together. Each chip can be optimized for specific functions, and the modular segmented architecture allows for more flexible space utilization compared to a monolithic single-chip design.

Inventive Principle:
Principle #1Segmentation

2Reliability

If grating couplers are used for light transfer between chips, then inter-chip optical coupling is achieved, but sensitivity to misalignment increases

Engineering Contradiction:
Improveoptical coupling efficiencyVSAvoidalignment precision requirement
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces an intermediary dielectric layer between the stacked chips that enables evanescent coupling of light. This intermediary structure facilitates optical interaction between adjacent chips through evanescent field coupling, which is less sensitive to alignment precision compared to grating couplers, as it does not require periodic structures or precise grating pitch matching.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the mechanical grating-based optical coupling system with an evanescent coupling mechanism that utilizes the exponential decay of electromagnetic fields in the dielectric layer. This substitution eliminates the need for precise mechanical alignment of grating structures while maintaining effective optical coupling.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution increases the capabilities of photonics chips by allowing inter-chip light transfer, enhancing available space for devices and reducing sensitivity to misalignment, thus improving data communication and computation systems.

Implementation Method 1

The second waveguide core is positioned adjacent to the ring resonator, enabling efficient light transfer between chips without the need for grating couplers

Methodology Applied
Scientific EffectEvanescent coupling:

Data Source

PatentUS12001056B2Light coupling between stacked photonics chips
Publication Date: 2024.06.04 GLOBALFOUNDRIES US INC
  • US12001056B2 patent drawing
  • US12001056B2 patent drawing
  • US12001056B2 patent drawing

AI summary

Structures including stacked photonics chips and methods of fabricating a structure including stacked photonics chips. The structure comprises a first chip including a first waveguide core, a ring resonator adjacent to a portion of the first waveguide core, and a first dielectric layer over the first waveguide core and the ring resonator. The first dielectric layer has a first surface. The structure further comprises a second chip including a second waveguide core and a second dielectric layer over the second waveguide core. The second dielectric layer has a second surface adjacent to the first surface of the first dielectric layer, and the second waveguide core is positioned adjacent to the ring resonator.