Stacked Silicon Photonics Packaging for Signal and Thermal Integrity

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Solution Overview

Problem

Designing and manufacturing high-density optoelectronic assemblies face challenges such as signal integrity, power integrity, thermal performance, electrical coupling, and optical coupling due to the close positioning of multiple integrated circuits, particularly in silicon photonics and electronic components.

Innovation Solution

Implementing flip-chip face-to-face die-stacked integrated silicon photonics with an interposer that mechanically and electrically couples electrical and optical integrated circuits, eliminating wire bonds and using LGA or BGA packaging, which supports co-packaging with electronic components like ASICs and CPUs, and allowing for removable optical interfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple integrated circuits are positioned close together to achieve high-density assembly, then productivity and device integration are improved, but signal integrity and power integrity deteriorate due to interference and coupling challenges

Engineering Contradiction:

Improveassembly densityVSAvoidsignal integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent transitions from planar arrangement of integrated circuits to a three-dimensional stacked configuration using flip-chip bonding. Electrical and optical integrated circuits are vertically stacked and bonded face-to-face, enabling high-density integration while maintaining signal integrity through controlled interconnect lengths and reduced electromagnetic interference compared to lateral routing.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces an interposer substrate as an intermediary component between the electrical and optical integrated circuits. The interposer provides controlled impedance routing, precise alignment features, and mechanical support, enabling reliable electrical coupling while maintaining signal integrity in the high-density stacked configuration.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Area of stationary object

If integrated circuits are positioned close together for high-density assembly, then area utilization is improved, but thermal performance deteriorates due to heat accumulation

Engineering Contradiction:

Improveassembly footprintVSAvoidthermal management

Core Design Contradiction:

Area of stationary objectVSTemperature

Solution Approach 1:

The patent employs vertical stacking of integrated circuits on the interposer substrate, moving from two-dimensional planar layout to three-dimensional configuration. This dimensional transition reduces the assembly footprint while distributing heat sources vertically, improving thermal management through enhanced heat dissipation pathways and reduced thermal coupling between adjacent circuits.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If wire bonds are used for electrical coupling, then ease of manufacture is improved, but mechanical integrity and signal integrity deteriorate due to bonding challenges and parasitic effects

Engineering Contradiction:

Improvecoupling methodVSAvoidmechanical integrity

Core Design Contradiction:

Ease of manufactureVSStrength

Solution Approach 1:

The patent replaces traditional wire bond mechanical coupling with direct flip-chip bonding of integrated circuit substrates to the interposer. This substitution eliminates wire bond parasitic inductance and resistance, improves mechanical integrity through direct substrate-to-substrate bonding, and maintains manufacturability through established flip-chip bonding processes.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Reliability

If tight coupling tolerances are maintained for electrical and optical coupling, then signal integrity is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvecoupling precisionVSAvoidalignment tolerance

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent uses the interposer substrate as a precision intermediary with integrated alignment features such as registration marks and mechanical locators. These features enable accurate alignment between electrical and optical integrated circuits during assembly, maintaining tight coupling tolerances for optimal signal integrity while reducing the overall manufacturing precision burden through standardized interfaces.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves mechanical integrity, signal and power integrity, thermal performance, and enables high-yield assembly with removable components for improved reliability and serviceability, while maintaining tight electrical and optical coupling tolerances.

Implementation Method 1

flip-chip bonding the stack assembly to an interposer

Methodology Applied

Scientific EffectFlip-chip bonding: Welding

Data Source

PatentUS12529853B2Photonic optoelectronic module packaging

Publication Date: 2026.01.20 II VI DELAWARE INC

AI summary

In one example, an optoelectronic module may include a stack assembly including an electrical integrated circuit and an optical integrated circuit electrically and mechanically coupled to one another, an interposer electrically and mechanically coupled to the stack assembly, and an optical connector to optically couple the optical integrated circuit with an array of optical fibers.