Stacked PIC-Switch ASIC Assembly for Shorter RF Trace Paths
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Solution Overview
Problem
Integrated photonic platforms require significant lengths of high-speed traces to connect components within the digital ASIC with optical inputs/outputs, which hinders efficient scalability and performance.
Innovation Solution
A stacked configuration of a photonic integrated circuit (PIC) and a switch ASIC, where the ASIC is mounted directly on top of the PIC, minimizing electrical connections and using low-speed through-silicon vias (TSVs) to reduce high-speed RF path lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If photonic components are arranged around the perimeter of the ASIC with long trace connections, then connectivity between optical inputs/outputs and digital components is achieved, but the trace length increases significantly causing performance degradation
Solution Approach 1:
The patent transitions from a 2D planar arrangement where photonic components are positioned around the perimeter of the ASIC to a 3D stacked configuration. The photonic integrated circuit is placed in a first layer and the ASIC in a second layer directly above it, enabling vertical interconnections through TSVs. This dimensional change dramatically reduces the horizontal trace length while maintaining all necessary connectivity between optical inputs/outputs and digital components.
2Ease of operation
If significant lengths of high speed traces are used to connect components, then component connectivity is maintained, but scalability is hindered
Solution Approach 1:
By stacking the photonic integrated circuit and ASIC vertically, the patent enables compact integration that scales more effectively. The reduced footprint in the horizontal plane allows for larger arrays of components to be integrated without proportionally increasing the overall device area, thereby improving scalability while maintaining full component connectivity through vertical TSV interconnections.
3Length of moving object
If photonic components and drivers are integrated on separate layers, then vertical electrical connections are minimized, but manufacturing complexity increases
Solution Approach 1:
The patent integrates drivers directly on the photonic integrated circuit layer rather than on a separate ASIC layer. This co-integration approach minimizes the need for long vertical electrical connections through TSVs, as drivers are positioned immediately adjacent to their corresponding photonic components. While this increases manufacturing complexity slightly, the benefit of minimized electrical connection length and improved signal integrity outweighs the additional fabrication steps required.
Data Source
AI summary
An integrated switch assembly having a stacked configuration, the integrated switch assembly comprising: a first layer, the first layer comprising a photonic integrated circuit, PIC; a second layer, the second layer comprising a switch ASIC; wherein the first layer is mounted onto a substrate and the second layer is mounted on top of the first layer.