Stacked PIC Semiconductor Package for High-Bandwidth Optical I/O
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high bandwidth for input/output optical signals and efficiently integrating multiple photonic integrated circuit (PIC) chips.
Innovation Solution
A semiconductor package design that includes a package substrate, an electronic integrated circuit (EIC) package, and multiple PIC chips stacked vertically, with each PIC chip featuring an upper groove for optical signal input/output and being electrically connected through a redistribution layer system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple PIC chips are integrated to increase bandwidth, then optical signal bandwidth is improved, but device complexity increases
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical stacking of PIC chips, utilizing the third dimension (height) to increase integration density. Multiple PIC chips are stacked in the vertical direction above the EIC package, allowing more components to be packed into a smaller footprint area while maintaining electrical connectivity through redistribution layers.
Solution Approach 2:
The patent implements a nested structure where PIC chips are stacked above the EIC package, which itself is mounted on a package substrate. The molding layer encapsulates the EIC chip and connects to redistribution layers, creating a hierarchical nested arrangement that integrates multiple functional blocks in a compact manner.
2Area of stationary object
If PIC chips are stacked vertically to increase integration density, then area utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates preliminary alignment features during the manufacturing process, including alignment marks and positioning structures on the package substrate and EIC package that guide the precise placement of subsequent PIC chips. The molding layer is formed with predetermined patterns that facilitate accurate alignment of stacked components.
Solution Approach 2:
The patent introduces intermediary alignment structures, such as alignment marks and positioning features, that mediate between different stacking layers. These intermediary elements enable precise alignment by providing reference points for positioning PIC chips relative to the EIC package and substrate, reducing the direct alignment precision requirements between distant components.
3Reliability
If redistribution layers are added to connect stacked PIC chips, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the redistribution layers, which simultaneously provide electrical connectivity between stacked PIC chips and EIC package, serve as alignment references, and act as part of the structural support. The molding layer also combines encapsulation, mechanical support, and electrical isolation functions, reducing the need for separate dedicated structures.
Solution Approach 2:
The redistribution layers are designed to perform multiple functions: electrical interconnection between different stacking levels, mechanical support for aligned positioning, and reference for alignment marks. This multi-functionality reduces the overall device complexity by eliminating the need for separate structures for each function.
Data Source
AI summary
An example semiconductor package includes a package substrate, an electronic integrated circuit (EIC) package mounted on the package substrate, and a plurality of photonic integrated circuit (PIC) chips stacked on the EIC package. Each PIC chip of the plurality of PIC chips includes an upper groove recessed inwards from an upper surface of the PIC chip and being open toward a first side surface of the PIC chip. The EIC package includes a lower redistribution layer on the package substrate, an EIC chip mounted on the lower redistribution layer, a molding layer surrounding the EIC chip, a through via passing through the molding layer in a vertical direction and electrically connected with the lower redistribution layer, and an upper redistribution layer on the through via.